Texas Instruments TM4C1294NCPDT User Manual

List of Tables
Table 1. Revision History .................................................................................................. 45
Table 2. Documentation Conventions ................................................................................ 49
Table 1-1. TM4C1294NCPDT Microcontroller Features .......................................................... 52
Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use ................................ 85
Table 2-2. Processor Register Map ....................................................................................... 86
Table 2-3. PSR Register Combinations ................................................................................. 92
Table 2-4. Memory Map ..................................................................................................... 103
Table 2-5. Memory Access Behavior ................................................................................... 107
Table 2-6. SRAM Memory Bit-Banding Regions ................................................................... 109
Table 2-7. Peripheral Memory Bit-Banding Regions ............................................................. 109
Table 2-8. Exception Types ................................................................................................ 115
Table 2-9. Interrupts .......................................................................................................... 116
Table 2-10. Exception Return Behavior ................................................................................. 123
Table 2-11. Faults ............................................................................................................... 124
Table 2-12. Fault Status and Fault Address Registers ............................................................ 125
Table 2-13. Cortex-M4F Instruction Summary ....................................................................... 127
Table 3-1. Core Peripheral Register Regions ....................................................................... 134
Table 3-2. Memory Attributes Summary .............................................................................. 138
Table 3-3. TEX, S, C, and B Bit Field Encoding ................................................................... 140
Table 3-4. Cache Policy for Memory Attribute Encoding ....................................................... 141
Table 3-5. AP Bit Field Encoding ........................................................................................ 141
Table 3-6. Memory Region Attributes for Tiva™ C Series Microcontrollers ............................. 142
Table 3-7. QNaN and SNaN Handling ................................................................................. 145
Table 3-8. Peripherals Register Map ................................................................................... 146
Table 3-9. Interrupt Priority Levels ...................................................................................... 171
Table 3-10. Example SIZE Field Values ................................................................................ 199
Table 4-1. JTAG_SWD_SWO Signals (128TQFP) ............................................................... 208
Table 4-2. JTAG Port Pins State after Power-On Reset or RST assertion .............................. 210
Table 4-3. JTAG Instruction Register Commands ................................................................. 216
Table 5-1. System Control & Clocks Signals (128TQFP) ...................................................... 220
Table 5-2. Reset Sources ................................................................................................... 221
Table 5-3. Clock Source Options ........................................................................................ 231
Table 5-4. Clock Source State Following POR ..................................................................... 231
Table 5-5. System Clock Frequency ................................................................................... 235
Table 5-6. System Divisor Factors for f
vco
=480 MHz ............................................................ 237
Table 5-7. Actual PLL Frequency ........................................................................................ 238
Table 5-8. Peripheral Memory Power Control ...................................................................... 243
Table 5-9. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 244
Table 5-10. MOSC Configurations ........................................................................................ 247
Table 5-11. System Control Register Map ............................................................................. 247
Table 5-12. MEMTIM0 Register Configuration versus Frequency ............................................ 277
Table 5-13. MOSC Configurations ........................................................................................ 281
Table 5-14. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 300
Table 5-15. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 303
Table 5-16. Module Power Control ........................................................................................ 451
Table 5-17. Module Power Control ........................................................................................ 453
17June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller

Texas Instruments TM4C1294NCPDT Specifications

General

Brand	Texas Instruments
Model	TM4C1294NCPDT
Category	Microcontrollers
Language	English