Texas Instruments TM4C1294NCPDT - Page 20

Table 16-3. UART Register Map ......................................................................................... 1173
Table 17-1. SSI Signals (128TQFP) .................................................................................... 1228
Table 17-2. QSSI Transaction Encodings ............................................................................ 1231
Table 17-3. SSInFss Functionality ...................................................................................... 1231
Table 17-4. Legacy Mode TI, Freescale SPI Frame Format Features .................................... 1233
Table 17-5. SSI Register Map ............................................................................................. 1243
Table 18-1. I2C Signals (128TQFP) .................................................................................... 1277
Table 18-2. Examples of I
2
C Master Timer Period Versus Speed Mode ................................. 1284
Table 18-3. Examples of I
2
C Master Timer Period in High-Speed Mode ................................ 1285
Table 18-4. Inter-Integrated Circuit (I
2
C) Interface Register Map ........................................... 1300
Table 18-5. Write Field Decoding for I2CMCS[6:0] ............................................................... 1308
Table 19-1. Controller Area Network Signals (128TQFP) ...................................................... 1357
Table 19-2. Message Object Configurations ........................................................................ 1363
Table 19-3. CAN Protocol Ranges ...................................................................................... 1371
Table 19-4. CANBIT Register Values .................................................................................. 1371
Table 19-5. CAN Register Map ........................................................................................... 1375
Table 20-1. Ethernet Signals (128TQFP) ............................................................................. 1409
Table 20-2. Enhanced Transmit Descriptor 0 (TDES0) ......................................................... 1414
Table 20-3. Enhanced Transmit Descriptor 1 (TDES1) ......................................................... 1417
Table 20-4. Enhanced Transmit Descriptor 2 (TDES2) ......................................................... 1418
Table 20-5. Enhanced Transmit Descriptor 3 (TDES3) ......................................................... 1418
Table 20-6. Enhanced Transmit Descriptor 6 (TDES6) ......................................................... 1418
Table 20-7. Enhanced Transmit Descriptor 7 (TDES7) ......................................................... 1418
Table 20-8. Enhanced Receive Descriptor 0 (RDES0) .......................................................... 1419
Table 20-9. RDES0 Checksum Offload bits ......................................................................... 1421
Table 20-10. Enhanced Receive Descriptor 1 (RDES1) .......................................................... 1422
Table 20-11. Enhanced Receive Descriptor 2 (RDES2) .......................................................... 1422
Table 20-12. Enhanced Receive Descriptor 3 (RDES3) .......................................................... 1422
Table 20-13. Enhanced Received Descriptor 4 (RDES4) ........................................................ 1422
Table 20-14. Enhanced Receive Descriptor 6 (RDES6) .......................................................... 1424
Table 20-15. Enhanced Receive Descriptor 7 (RDES7) .......................................................... 1424
Table 20-16. TX MAC Flow Control ...................................................................................... 1437
Table 20-17. RX MAC Flow Control ...................................................................................... 1437
Table 20-18. VLAN Match Status .......................................................................................... 1450
Table 20-19. CRC Replacement Based on Bit 27 and Bit 24 of TDES0 ................................... 1452
Table 20-20. Forced Mode Configurations ............................................................................. 1458
Table 20-21. Advertised Mode Configurations ....................................................................... 1459
Table 20-22. EMACPC to PHY Register Mapping .................................................................. 1465
Table 20-23. Ethernet Register Map ..................................................................................... 1467
Table 20-24. PPSCTRL Bit Field Values ............................................................................... 1549
Table 21-1. USB Signals (128TQFP) .................................................................................. 1646
Table 21-2. List of Registers ............................................................................................... 1647
Table 22-1. Analog Comparators Signals (128TQFP) ........................................................... 1654
Table 22-2. Internal Reference Voltage and ACREFCTL Field Values ................................... 1656
Table 22-3. Analog Comparator Voltage Reference Characteristics, V
DDA
= 3.3V, EN= 1, and
RNG = 0 .......................................................................................................... 1657
Table 22-4. Analog Comparator Voltage Reference Characteristics, V
DDA
= 3.3V, EN= 1, and
RNG = 1 .......................................................................................................... 1658
June 18, 201420
Texas Instruments-Production Data
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