Texas Instruments TM4C1294NCPDT User Manual

Table 18-2. Examples of I
2
C Master Timer Period Versus Speed Mode (continued)
Fast Mode
Plus
Timer
Period
Fast ModeTimer PeriodStandard ModeTimer PeriodSystem Clock
1000 Kbps0x01400 Kbps0x04100 Kbps0x1340 MHz
833 Kbps0x02357 Kbps0x06100 Kbps0x1850 MHz
1000 Kbps0x03400 Kbps0x09100 Kbps0x2780 MHz
1000 Kbps0x04385 Kbps0x0C100 Kbps0x31100 MHz
1000 Kbps0x5400 Kbps0xE100 Kbps0x3B120 MHz
18.3.2.2 High-Speed Mode
The TM4C1294NCPDT I
2
C peripheral has support for High-speed operation as both a master and
slave. High-Speed mode is configured by setting the HS bit in the I
2
C Master Control/Status
(I2CMCS) register. High-Speed mode transmits data at a high bit rate with a 66.6%/33.3% duty
cycle, but communication and arbitration are done at Standard, Fast mode, or Fast-mode plus
speed, depending on which is selected by the user. When the HS bit in the I2CMCS register is set,
current mode pull-ups are enabled.
The clock period can be selected using the equation below, but in this case, SCL_LP=2 and
SCL_HP=1.
SCL_PERIOD = 2 × (1 + TIMER_PRD) × (SCL_LP + SCL_HP) × CLK_PRD
So for example:
CLK_PRD = 25 ns
TIMER_PRD = 1
SCL_LP=2
SCL_HP=1
yields a SCL frequency of:
1/T = 3.33 Mhz
Table 18-3 on page 1285 gives examples of timer period and system clock in High-Speed mode. Note
that the HS bit in the I2CMTPR register needs to be set for the TPR value to be used in High-Speed
mode.
Table 18-3. Examples of I
2
C Master Timer Period in High-Speed Mode
Transmission ModeTimer PeriodSystem Clock
3.33 Mbps0x0140 MHz
2.77 Mbps0x0250 MHz
3.33 Mbps0x0380 MHz
When operating as a master, the protocol is shown in Figure 18-7. The master is responsible for
sending a master code byte in either Standard (100 Kbps) or Fast-mode (400 Kbps) before it begins
transferring in High-speed mode. The master code byte must contain data in the form of 0000.1XXX
and is used to tell the slave devices to prepare for a High-speed transfer. The master code byte
should never be acknowledged by a slave since it is only used to indicate that the upcoming data
is going to be transferred at a higher data rate. To send the master code byte for a standard
high-speed transfer, software should place the value of the master code byte into the I2CMSA
register and write the I2CMCS register with a value of 0x13. If a high-speed burst transfer is required,
1285June 18, 2014
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TM4C1294NCPDT Microcontroller

Texas Instruments TM4C1294NCPDT Specifications

General

Brand	Texas Instruments
Model	TM4C1294NCPDT
Category	Microcontrollers
Language	English