DescriptionResetTypeNameBit/Field
Odd Nibble TXER Detection Disable
This bit is sampled on the deassertion of the PHY reset signal and is
used as the default for the ODDNDETDIS bit of the Ethernet PHY
Configuration 2 (EPHYCFG2) register, PHY offset 0x00A.
0RONIBDETDIS24
RXER Detection During Idle
This bit is sampled on the deassertion of the PHY reset signal and is
used as the default for the RXERRIDLE bit of the Ethernet PHY
Configuration 2 (EPHYCFG2) register, PHY offset 0x00A.
1RWRXERIDLE23
Isolate MII in Link Loss
This bit is sampled on the deassertion of the PHY reset signal and is
used as the default for the ISOMIILL bit of the Ethernet PHY
Configuration 2 (EPHYCFG2) register, PHY offset 0x00A.
0RWISOMIILL22
Link Loss Recovery
This bit is sampled on the deassertion of the PHY reset signal and is
used as the default for the LLR bit of the Ethernet PHY Configuration
1 (EPHYCFG1) register, PHY offset 0x009.
0RWLRR21
TDR Auto Run
This bit is sampled on the deassertion of the PHY reset signal and is
used as the default for the TDRAR bit of the Ethernet PHY Configuration
1 (EPHYCFG1) register, PHY offset 0x009.
0RWTDRRUN20
Fast Link Down Mode
These bits are sampled on the deassertion of the PHY reset signal and
are used as the default for the FLDWNM bit field of the Ethernet PHY
Configuration 3 (EPHYCFG3) register, PHY offset 0x00B.
0RWFASTLDMODE19:15
Polarity Swap
This bit is sampled on the deassertion of the PHY reset signal and is
used as the default for the POLSWAP bit of the Ethernet PHY
Configuration 3 (EPHYCFG3) register PHY offset 0x00B.
0RWPOLSWAP14
MDI Swap
This bit is sampled on the deassertion of the PHY reset signal and is
used as the default for the MDIMDIXS bit of the Ethernet PHY
Configuration 3 (EPHYCFG3) register, PHY offset 0x00B.
0RWMDISWAP13
Robust Auto MDI-X
This bit is sampled on the deassertion of the PHY reset signal and is
used as the default for the RAMDIX bit of the Ethernet PHY
Configuration 1 (EPHYCFG1) register, PHY offset 0x009.
0RWRBSTMDIX12
Fast Auto MDI-X
This bit is sampled on the deassertion of the PHY reset signal and is
used as the default for the FAMDIX bit of the Ethernet PHY
Configuration 1 (EPHYCFG1) register, PHY offset 0x009.
0ROFASTMDIX11
1583June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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