DescriptionResetTypeNameBit/Field
MDIX Enable
This bit is sampled on the deassertion of the PHY reset signal and is
used to determine whether automatic MDI/MDIX crossover is enabled.
DescriptionValue
Disable automatic cross-over.0
Enable automatic cross-over.1
1RWMDIXEN10
Fast RXDV Detection
This bit is sampled on the deassertion of the PHY reset signal and is
used to select whether fast RXDV detection is enabled in the PHY.
DescriptionValue
Disable fast RXDV detection.0
Enable fast RXDV detection.1
0RWFASTRXDV9
FAST Link-Up in Parallel Detect
This bit is sampled on the deassertion of the PHY reset signal and is
used as the default value for the FLUPPD bit of the Ethernet PHY
Configuration 2 (EPHYCFG2) register, PHY offset 0x00A.
0RWFASTLUPD8
Extended Full Duplex Ability
This bit is sampled on the deassertion of the PHY reset signal and is
used as the default value for the EXTFD bit of the Ethernet PHY
Configuration 2 (EPHYCFG2) register, PHY offset 0x00A.
0RWEXTFD7
Fast Auto Negotiation Enable
This bit is sampled on the deassertion of the PHY reset signal and is
used as the default for the FASTANEN bit of the Ethernet PHY
Configuration 1 (EPHYCFG1) register, PHY offset 0x009.
0RWFASTANEN6
Fast Auto Negotiation Select
These bits are sampled on the deassertion of the PHY reset signal and
are used as the defaults for the FANSEL bit field of the Ethernet PHY
Configuration 1 (EPHYCFG1) register, PHY offset 0x009.
0RWFASTANSEL5:4
Auto Negotiation Enable
This bit is sampled on the deassertion of the PHY reset signal and is to
select whether auto-negotiation is enabled.
DescriptionValue
Auto-negotiation disabled.0
Auto-negotiation enabled.1
1RWANEN3
June 18, 20141584
Texas Instruments-Production Data
Ethernet Controller
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