DescriptionResetTypeNameBit/Field
QSSI Transmit FIFO Raw Interrupt Status
DescriptionValue
No interrupt.0
The transmit FIFO is half empty or less.1
This bit is cleared when the transmit FIFO is more than half full.
1ROTXRIS3
QSSI Receive FIFO Raw Interrupt Status
DescriptionValue
No interrupt.0
The receive FIFO is half full or more.1
This bit is cleared when the receive FIFO is less than half full.
0RORXRIS2
QSSI Receive Time-Out Raw Interrupt Status
DescriptionValue
No interrupt.0
The receive time-out has occurred.1
This bit is cleared when a 1 is written to the RTIC bit in the SSI Interrupt
Clear (SSIICR) register.
0RORTRIS1
QSSI Receive Overrun Raw Interrupt Status
DescriptionValue
No interrupt.0
The receive FIFO has overflowed1
This bit is cleared when a 1 is written to the RORIC bit in the SSI
Interrupt Clear (SSIICR) register.
0RORORRIS0
June 18, 20141256
Texas Instruments-Production Data
Quad Synchronous Serial Interface (QSSI)