DescriptionResetTypeNameBit/Field
Read Stall Error
DescriptionValue
The Read Stalled error interrupt is disabled. Reads behave as
normal and are stalled until any preceding writes have completed
and the read has returned a result.
0
This bit enables the Read Stalled error interrupt (RSTALL in the
EPIEISC register) to be generated when a read is attempted
and the WFIFO is not empty. The read is still stalled during the
time the WFIFO drains, but this error notifies the application
that this excess delay has occurred.
1
Note that the configuration of this bit has no effect on non-blocking reads.
0RWRSERR16
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved15:7
Write FIFO
DescriptionValue
Interrupt is triggered while WRFIFO is empty. It will be
deasserted when not empty. This encoding is optimized for
burst of 4 writes.
0x0
reserved0x1
Interrupt is triggered until there are only two slots available.
Thus, trigger is deasserted when there are two WRFIFO
entries present. This configuration is optimized for bursts of
2.
0x2
Interrupt is triggered until there is one WRFIFO entry
available. This configuration expects only single writes.
0x3
Trigger interrupt when WRFIFO is not full, meaning trigger
will continue to assert until there are four entries in the
WRFIFO.
0x4
reserved0x5-0x7
0x3RWWRFIFO6:4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved3
Read FIFO
This field configures the trigger point for the NBRFIFO.
DescriptionValue
reserved0x0
Trigger when there are 1 or more entries in the NBRFIFO.0x1
Trigger when there are 2 or more entries in the NBRFIFO.0x2
Trigger when there are 4 or more entries in the NBRFIFO.0x3
Trigger when there are 6 or more entries in the NBRFIFO.0x4
Trigger when there are 7 or more entries in the NBRFIFO.0x5
Trigger when there are 8 entries in the NBRFIFO.0x6
reserved0x7
0x3RWRDFIFO2:0
June 18, 2014904
Texas Instruments-Production Data
External Peripheral Interface (EPI)
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