DescriptionResetTypeNameBit/Field
5th Sample Interrupt Enable
DescriptionValue
The raw interrupt is not asserted to the interrupt controller.0
The raw interrupt signal (INR0 bit) is asserted at the end of the
fifth sample's conversion. If the MASK0 bit in the ADCIM register
is set, the interrupt is promoted to the interrupt controller.
1
It is legal to have multiple samples within a sequence generate interrupts.
0RWIE418
5th Sample is End of Sequence
DescriptionValue
Another sample in the sequence is the final sample.0
The fifth sample is the last sample of the sequence.1
It is possible to end the sequence on any sample position. Software
must set an ENDn bit somewhere within the sequence. Samples defined
after the sample containing a set ENDn bit are not requested for
conversion even though the fields may be non-zero.
0RWEND417
5th Sample Differential Input Select
DescriptionValue
The analog inputs are not differentially sampled.0
The analog input is differentially sampled. The corresponding
ADCSSMUXn nibble must be set to the pair number "i", where
the paired inputs are "2i and 2i+1".
1
Because the temperature sensor does not have a differential option,
this bit must not be set when the TS4 bit is set.
0RWD416
4th Sample Temp Sensor Select
DescriptionValue
The input pin specified by the ADCSSMUXn register is read
during the fourth sample of the sample sequence.
0
The temperature sensor is read during the fourth sample of the
sample sequence.
1
0RWTS315
4th Sample Interrupt Enable
DescriptionValue
The raw interrupt is not asserted to the interrupt controller.0
The raw interrupt signal (INR0 bit) is asserted at the end of the
fourth sample's conversion. If the MASK0 bit in the ADCIM
register is set, the interrupt is promoted to the interrupt controller.
1
It is legal to have multiple samples within a sequence generate interrupts.
0RWIE314
June 18, 20141114
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
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