DescriptionResetTypeNameBit/Field
UART Enable FIFOs
DescriptionValue
The FIFOs are disabled (Character mode). The FIFOs become
1-byte-deep holding registers.
0
The transmit and receive FIFO buffers are enabled (FIFO mode).1
0RWFEN4
UART Two Stop Bits Select
DescriptionValue
One stop bit is transmitted at the end of a frame.0
Two stop bits are transmitted at the end of a frame. The receive
logic does not check for two stop bits being received.
When in 7816 smartcard mode (the SMART bit is set in the
UARTCTL register), the number of stop bits is forced to 2.
1
0RWSTP23
UART Even Parity Select
DescriptionValue
Odd parity is performed, which checks for an odd number of 1s.0
Even parity generation and checking is performed during
transmission and reception, which checks for an even number
of 1s in data and parity bits.
1
This bit has no effect when parity is disabled by the PEN bit.
0RWEPS2
UART Parity Enable
DescriptionValue
Parity is disabled and no parity bit is added to the data frame.0
Parity checking and generation is enabled.1
0RWPEN1
UART Send Break
DescriptionValue
Normal use.0
A Low level is continually output on the UnTx signal, after
completing transmission of the current character. For the proper
execution of the break command, software must set this bit for
at least two frames (character periods).
1
0RWBRK0
1187June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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