Texas Instruments TM4C1294NCPDT User Manual

DescriptionResetTypeNameBit/Field
UART Receive Time-Out Raw Interrupt Status
DescriptionValue
No interrupt0
A receive time out has occurred.1
This bit is cleared by writing a 1 to the RTIC bit in the UARTICR register.
For receive timeout, the RTIM bit in the UARTIM register must be set
to see the RTRIS status.
0RORTRIS6
UART Transmit Raw Interrupt Status
DescriptionValue
No interrupt0
If the EOT bit in the UARTCTL register is clear, the transmit
FIFO level has passed through the condition defined in the
UARTIFLS register.
If the EOT bit is set, the last bit of all transmitted data and flags
has left the serializer.
1
This bit is cleared by writing a 1 to the TXIC bit in the UARTICR register
or by writing data to the transmit FIFO until it becomes greater than the
trigger level, if the FIFO is enabled, or by writing a single byte if the FIFO
is disabled.
0ROTXRIS5
UART Receive Raw Interrupt Status
DescriptionValue
No interrupt0
The receive FIFO level has passed through the condition defined
in the UARTIFLS register.
1
This bit is cleared by writing a 1 to the RXIC bit in the UARTICR register
or by reading data from the receive FIFO until it becomes less than the
trigger level, if the FIFO is enabled, or by reading a single byte if the
FIFO is disabled.
0RORXRIS4
UART Data Set Ready Modem Raw Interrupt Status
DescriptionValue
No interrupt0
Data Set Ready used for software flow control.1
This bit is cleared by writing a 1 to the DSRIC bit in the UARTICR
register.
0RODSRRIS3
UART Data Carrier Detect Modem Raw Interrupt Status
DescriptionValue
No interrupt0
Data Carrier Detect used for software flow control.1
This bit is cleared by writing a 1 to the DCDIC bit in the UARTICR
register.
0RODCDRIS2
June 18, 20141200
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)

Texas Instruments TM4C1294NCPDT Specifications

General

Brand	Texas Instruments
Model	TM4C1294NCPDT
Category	Microcontrollers
Language	English