18.3.1.9 Glitch Suppression in Multi-Master Configuration
When a multi-master configuration is being used, the PULSEL bit in the I2CMTPR register can be
programmed to provide glitch suppression on the SCL and SDA lines and assure proper signal
values. The glitch suppression value is in terms of buffered system clocks. Note that all signals will
be delayed internally when glitch suppression is nonzero. For example, if PULSEL is set to 0x7, 31
clocks should be added onto the calculation for the expected transaction time.
18.3.1.10 SMBus Operation
The SMBus interface is based on the I
2
C protocol; however, some differences exist between the
two. These differences must be handled through software in order to make sure the SMBus protocol,
including timing specifications, is met. Note that the SMBus 2.0 specification limits the maximum
frequency of the interface to 100 KHz, as a result, I
2
C Standard speed operation is used for SMBus.
The SMBus/ I
2
C slave can extend the transaction if it is not ready by pulling the clock low. The
SMbus specification allows the maximum timeout for such elongated transaction to be between 25
to 35 ms. The I
2
C specification does not have this requirement. The I
2
C module supports a
programmable count to support clock-low timeout for the master to error out and take appropriate
action as required. This feature is explained in “Clock Low Timeout (CLTO)” on page 1281. Note that
if transactions are extended, a timeout period should be programmed in the I2CMCLKOCNT register,
and the CLKRIS bit in the I2CMRIS register should not be masked.
Unlike the I
2
C slave, the SMBus slave must respond with an ACK response to its address regardless
of whether it is ready or not. As a result, the I
2
C slave sends an ACK response to its address and
a NACK response on the data byte if it is not ready. The ARBLST bit in the I2CMCS register is set
if there were any issues with the transfer. In addition, the slave can send a NACK at any time to
force the master to stop sending additional bytes.
The I
2
C Interface supports µDMA for efficient data handling. The µDMA operation needs FIFOs to
be enabled for appropriate transfer type to perform I
2
C Master for burst transfers and all types of
Slave transfers. The I
2
C interface is supported by two channels, one for Rx (I
2
C to Memory) and
one for Tx (Memory to I
2
C) transfers.. See“FIFO and µDMA Operation” on page 1287 for more
information.
Quick Command
Quick Command is a simple, compact SMBus protocol that sends an address and 1-bit of data in
the R/S bit of the I
2
C header byte to communicate a command to the slave, typically a "turn off" or
"turn on". The I
2
C master peripheral has the ability to send a Quick Command by writing the target
address and R/S value into the I2CMSA register followed by a write to I2CMCS with a value of
0x27. SMBus requires the slave to be able to accept and process commands and the master to
generate the Quick Command transactions. The master also has the capability to stop the transaction
after acknowledgement from a slave.
The I
2
C slave peripheral requires special handling when a Quick Command is sent. In the case
where a master sends a Quick Command with the R/S (data) bit cleared, the QCMDST bit in I2CSCSR
is set, and the QCMDRW bit shows the data value (which in this case is 0) when the STOPRIS bit is
set in I2CSRIS and the STOP interrupt is asserted. In this scenario, a DATARIS interrupt bit is not
set. When the master sends a Quick Command with the R/S (data) bit set, the DATARIS bit is set
to notify the slave to write a data byte to I2CSDR in which bit 7 is set. A “dummy write” of 0xFF to
the I2CSDR register is recommended. After the write to I2CSDR, the STOP interrupt is asserted
and the QCMDST and QCMDRW bits are set in the I2CSCSR register to indicate that a quick command
read occurred and the last transaction was a Quick Command. Therefore, when the slave must
1283June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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