DescriptionResetTypeNameBit/Field
Receive FIFO Request Raw Interrupt Status
DescriptionValue
No interrupt0
The trigger value for the FIFO has been reached and a RX FIFO
Request interrupt is pending.
1
This bit is cleared by writing a 1 to the RXIC bit in the I2CSICR register.
0RORXRIS6
Transmit Request Raw Interrupt Status
DescriptionValue
No interrupt0
The trigger value for the FIFO has been reached and a TX FIFO
Request interrupt is pending.
1
This bit is cleared by writing a 1 to the TXIC bit in the I2CSICR register.
0ROTXRIS5
Transmit DMA Raw Interrupt Status
DescriptionValue
No interrupt.0
A transmit DMA complete interrupt is pending.1
This bit is cleared by writing a 1 to the DMATXIC bit in the I2CSICR
register.
0RODMATXRIS4
Receive DMA Raw Interrupt Status
DescriptionValue
No interrupt.0
A receive DMA complete interrupt is pending.1
This bit is cleared by writing a 1 to the DMARXIC bit in the I2CSICR
register.
0RODMARXRIS3
Stop Condition Raw Interrupt Status
DescriptionValue
No interrupt.0
A STOP condition interrupt is pending.1
This bit is cleared by writing a 1 to the STOPIC bit in the I2CSICR
register.
0ROSTOPRIS2
Start Condition Raw Interrupt Status
DescriptionValue
No interrupt.0
A START condition interrupt is pending.1
This bit is cleared by writing a 1 to the STARTIC bit in the I2CSICR
register.
0ROSTARTRIS1
1339June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller