DescriptionResetTypeNameBit/Field
Receive FIFO Request Interrupt Mask
DescriptionValue
No interrupt.0
An unmasked Receive FIFO Request interrupt was signaled
and is pending.
1
This bit is cleared by writing a 1 to the RXIC bit in the I2CSICR register.
0RORXMIS6
Transmit FIFO Request Interrupt Mask
DescriptionValue
No interrupt.0
An unmasked Transmit FIFO Request interrupt was signaled
and is pending.
1
This bit is cleared by writing a 1 to the TXIC bit in the I2CSICR register.
0ROTXMIS5
Transmit DMA Masked Interrupt Status
DescriptionValue
An interrupt has not occurred or is masked.0
An unmasked transmit DMA complete interrupt was signaled is
pending.
1
This bit is cleared by writing a 1 to the DMATXIC bit in the I2CSICR
register.
0RODMATXMIS4
Receive DMA Masked Interrupt Status
DescriptionValue
An interrupt has not occurred or is masked.0
An unmasked receive DMA complete interrupt was signaled is
pending.
1
This bit is cleared by writing a 1 to the DMARXIC bit in the I2CSICR
register.
0RODMARXMIS3
Stop Condition Masked Interrupt Status
DescriptionValue
An interrupt has not occurred or is masked.0
An unmasked STOP condition interrupt was signaled is pending.1
This bit is cleared by writing a 1 to the STOPIC bit in the I2CSICR
register.
0ROSTOPMIS2
June 18, 20141342
Texas Instruments-Production Data
Inter-Integrated Circuit (I
2
C) Interface