Table 20-8. Enhanced Receive Descriptor 0 (RDES0) (continued)
DescriptionBit
FL: Frame Length
These bits indicate the byte length of the received frame that was transferred to the system memory. This field
is valid when the Last Descriptor (RDES0[8]) is set and either the Descriptor Error (RDES0[14]) or the Overflow
Error bit (RDES0[11]) is clear.
When the Last Descriptor bit is not set, this field indicates the accumulated number of bytes that have been
transferred for the current frame. The inclusion of CRC length in the frame length depends on the settings of
CRC configuration bits, ACS and CST in the EMACCFG register.
29:16
ES: Error Summary
Indicates the logical OR of the following bits:
■ RDES0[14]: Descriptor Error
■ RDES0[11]: Overflow Error
■ RDES0[7]: IPC Checksum (Type 2) or Giant Frame
■ RDES0[6]: Late Collision
■ RDES0[4]: Watchdog Timeout
■ RDES0[3]: Receive Error
■ RDES0[1]: CRC Error
■ RDES[4:3]: IP Header or Payload Error
This field is valid only when the Last Descriptor (RDES0[8]) is set.
15
DE: Descriptor Error
When set, this bit indicates a frame truncation caused by a frame that does not fit within the current descriptor
buffers, and that the DMA does not own the Next Descriptor. The frame is truncated. This field is valid only when
the Last Descriptor (RDES0[8]) is set.
14
SAF: Source Address Filter Fail
When set, this bit indicates that the SA field of frame failed the SA Filter in the MAC.
13
LE: Length Error
When set, this bit indicates that the actual length of the frame received and the Length/Type field do not match.
This bit is valid only when the Frame Type (RDES0[5]) bit is reset. Length error status is not valid when CRC
error is present.
12
OE: Overflow Error
When set, this bit indicates that the received frame is damaged because of buffer overflow in RX FIFO.
Note: This bit is set only when the DMA transfers a partial frame to the application. This happens only when
the RX FIFO is operating in the threshold mode. In the store-and-forward mode, all partial frames are
dropped completely in RX FIFO.
11
VLAN: VLAN Tag
When set, this bit indicates that the frame pointed to by this descriptor is a VLAN frame tagged by the MAC. The
VLAN tagging depends on checking VLAN fields of the received frame configured in the Ethernet MAC VLAN
Tag (EMACVLANTG) register, offset 0x01C
10
FS: First Descriptor
When set, this bit indicates that this descriptor contains the first buffer of the frame. If the size of the first buffer
is 0, the second buffer contains the beginning of the frame. If the size of the second buffer is also 0, the next
Descriptor contains the beginning of the frame.
9
LS: Last Descriptor
When set, this bit indicates that the buffers pointed to by this descriptor are the last buffers of the frame.
8
June 18, 20141420
Texas Instruments-Production Data
Ethernet Controller
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