DescriptionResetTypeNameBit/Field
Disable Receive Own
When this bit is set, the MAC disables the reception of frames while
transmitting in half-duplex mode.
When this bit is clear, the MAC receives all packets that are given by
the PHY while transmitting.
DescriptionValue
All packets are received by MAC.0
Disable reception of frames.1
Note: This bit is not applicable if the MAC is operating in full-duplex
mode.
0RWDRO13
Loopback Mode
When this bit is set, the MAC operates in the loopback mode at the MII.
The MII Receive clock input, EN0RXCK, is required for the loopback to
work properly, because the Transmit clock is not looped-back internally.
DescriptionValue
MAC does not operate in loopback mode.0
MAC operates in loopback mode.1
0RWLOOPBM12
Duplex Mode
When this bit is set, the MAC operates in the full-duplex mode where it
can transmit and receive simultaneously.
DescriptionValue
MAC does not operate in full-duplex mode.0
MAC operates in full-duplex mode.1
0RWDUPM11
Checksum Offload
DescriptionValue
The checksum offload function in the receiver is disabled and
the corresponding PCE and IP HCE status bits in the frame
status are always cleared.
0
Checksum Offload Enable
Setting this bit enables the IPv4 header checksum checking
and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum
checking.
1
0x0RWIPC10
June 18, 20141474
Texas Instruments-Production Data
Ethernet Controller
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