Register 24: Ethernet MAC MMC Receive Raw Interrupt Status
(EMACMMCRXRIS), offset 0x104
The MAC MMC Receive Interrupt (EMACMMCRXRIS) register maintains the interrupts that are
generated when the following happens:
■ Receive statistic counters reach half of their maximum values (0x8000.0000 for 32-bit counter
and 0x8000 for 16-bit counter).
■ Receive statistic counters cross their maximum values (0xFFFF.FFFF for 32-bit counter and
0xFFFF for 16-bit counter).
When the Counter Stop Rollover (CNTSTPRO bit) in the MAC MMC Control (EMACMMCCTRL)
register is set, interrupts are set but the counter remains at all-ones. The EMACMMCRXRIS register
is a 32-bit wide register. An interrupt bit is cleared when the respective MMC counter that caused
the interrupt is read. The least significant byte lane (bits[7:0]) of the respective counter must be read
in order to clear the interrupt bit.
Ethernet MAC MMC Receive Raw Interrupt Status (EMACMMCRXRIS)
Base 0x400E.C000
Offset 0x104
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reservedUCGFreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
GBFreservedCRCERRALGNERRreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:18
MMC Receive Unicast Good Frame Counter Interrupt Status
DescriptionValue
The receive Ethernet MAC Receive Frame Count for Good
Unicast Frames (EMACRXCNTGUNI) register has not reached
half of the maximum value or the maximum value.
0
The receive Ethernet MAC Receive Frame Count for Good
Unicast Frames (EMACRXCNTGUNI) register has reached
half of the maximum value or the maximum value.
1
0x0ROUCGF17
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved16:7
1515June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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