DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved7:6
Addend Register Update
DescriptionValue
No effect.0
When set, the content of the Timestamp Addend register is
updated in the PTP block for fine correction. This is cleared
when the update is completed. This register bit should be zero
before setting it.
1
0x0RWADDREGUP5
Timestamp Interrupt Trigger Enable
DescriptionValue
No effect.0
The timestamp interrupt is generated when the System Time
becomes greater than the value written in the Ethernet MAC
Target Time Seconds/Nanoseconds
(EMACTARGSEC/EMACTARGNANO) registers. This bit is
reset after the generation of the Timestamp Trigger Interrupt.
1
0x0RWINTTRIG4
Timestamp Update
This bit should be read zero before updating it. This bit is reset when
the update is completed in hardware. The Timestamp Higher Word
register is not updated.
DescriptionValue
No effect.0
When set, the system time is updated (added or subtracted)
with the value specified in EMACTIMSECU (System Time -
Seconds Update Register) and EMACTIMNANOU (System
Time - Nanoseconds Update Register).
1
0x0RWTSUPDT3
Timestamp Initialize
This bit should read zero before updating it.
DescriptionValue
This bit is reset when the initialization is complete.0x0
The system time is initialized (overwritten) with the value
specified in the Ethernet MAC System Time-Seconds Update
(EMACTIMSECU) and the Ethernet MAC System
Time-Nanoseconds Update (EMACTIMNANOU) registers.
0x1
0x0RWTSINIT2
June 18, 20141536
Texas Instruments-Production Data
Ethernet Controller
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