DescriptionResetTypeNameBit/Field
Power Down
Setting this bit powers down the PHY. Only minimal register functionality
is enabled during the power down condition.
DescriptionValue
Normal operation0
Power-down modes are enabled: General Power Down Mode,
Active Sleep Mode and Passive Sleep Mode (see Ethernet
PHY Specific Control (EPHYSCR) register, offset 0x011.
1
0RWPWRDWN11
Port Isolate
DescriptionValue
Normal operation.0
Isolates the Port from the MII with the exception of the serial
management.
1
0RWISOLATE10
Restart Auto-Negotiation
DescriptionValue
Normal operation.0
Auto-Negotiation process is re-initiated. If Auto-Negotiation is
disabled (ANEN = 0), this bit is ignored. This bit is self-clearing
and returns a value of 1 until Auto-Negotiation is initiated,
whereupon it self-clears. Operation of the Auto-Negotiation
process is not affected by the management entity clearing this
bit..
1
0RWRESTARTAN9
Duplex Mode
When auto-negotiation is disabled writing to this bit allows the port-duplex
capability to be selected.
DescriptionValue
Half Duplex operation.0
Full Duplex Operation1
1RWDUPLEXM8
Collision Test
When set, this bit causes the EN0COL signal to be asserted in response
to the assertion of EN0TXEN within 512 bit times. The EN0COL signal is
deasserted within four bit times in response to the deassertion of
EN0TXEN.
DescriptionValue
Normal operation0
Collision test enabled.1
0RWCOLLTST7
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved6:0
1591June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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