DescriptionResetTypeNameBit/Field
PAUSE Support for Full Duplex Links
The PAUSE bit indicates that the device is capable of providing the
symmetric PAUSE functions as defined in Annex 31B.
Encoding and resolution of PAUSE bits is defined in IEEE 802.3 Annex
28B, Tables 28B-2 and 28B-3, respectively. Pause resolution status is
reported in the Ethernet PHY Control (EPHYCTL)register.
DescriptionValue
MAC PAUSE not implemented0
MAC PAUSE implemented. Advertise that the MAC has
implemented both the optional MAC control sub-layer and the
pause function as specified in clause 31 and annex 31B of
802.3u.
1
0RWPAUSE10
100Base-T4 Support
DescriptionValue
100Base-T4 not supported by the internal PHY.0
100Base-T4 is supported by the internal PHY.1
0RO100BT49
100Base-TX Full Duplex Support
DescriptionValue
100Base-TX Full Duplex not supported by the internal PHY.0
100Base-TX Full Duplex is supported by the internal PHY.1
1RW100BTXFD8
100Base-TX Support
DescriptionValue
100Base-TX not supported by the internal PHY.0
100Base-TX is supported by the internal PHY.1
1RW100BTX7
10Base-T Full Duplex Support
DescriptionValue
10Base-T Full Duplex not supported by the internal PHY.0
10Base-T Full Duplex is supported by the internal PHY.1
1RW10BTFD6
10Base-T Support
DescriptionValue
10Base-T not supported by the internal PHY.0
10Base-T is supported by the internal PHY.1
1RW10BT5
Protocol Selection
These bits contain the binary encoded protocol selector supported by
this port. 0x1 indicates that this device supports IEEE 802.3u.
0x1RWSELECT4:0
June 18, 20141598
Texas Instruments-Production Data
Ethernet Controller
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