DescriptionResetTypeNameBit/Field
Minimum Fault Period
This bit specifies that the PWM generator enables a one-shot counter
to provide a minimum fault condition period.
The timer begins counting on the rising edge of the fault condition to
extend the condition for a minimum duration of the count value. The
timer ignores the state of the fault condition while counting.
The minimum fault delay is in effect only when the MINFLTPER bit is
set. If a detected fault is in the process of being extended when the
MINFLTPER bit is cleared, the fault condition extension is aborted.
The delay time is specified by the PWMnMINFLTPER register MFP field
value. The effect of this is to pulse stretch the fault condition input.
The delay value is defined by the PWM clock period. Because the fault
input is not synchronized to the PWM clock, the period of the time is
PWMClock * (MFP value + 1) or PWMClock * (MFP value + 2).
The delay function makes sense only if the fault source is unlatched. A
latched fault source makes the fault condition appear asserted until
cleared by software and negates the utility of the extend feature. It
applies to all fault condition sources as specified in the FLTSRC field.
DescriptionValue
The FAULT input deassertion is unaffected.0
The PWMnMINFLTPER one-shot counter is active and extends
the period of the fault condition to a minimum period.
1
Note: When using an ADC digital comparator as a fault source, the
LATCH and MINFLTPER bits in the PWMnCTL register should
be set to 1 to ensure trigger assertions are captured.
0RWMINFLTPER17
Fault Condition Source
DescriptionValue
The Fault condition is determined by the Fault0 input.0
The Fault condition is determined by the configuration of the
PWMnFLTSRC0 and PWMnFLTSRC1 registers.
1
0RWFLTSRC16
PWMnDBFALL Update Mode
DescriptionValue
Immediate
The PWMnDBFALL register value is immediately updated on
a write.
0x0
Reserved0x1
Locally Synchronized
Updates to the register are reflected to the generator the next
time the counter is 0.
0x2
Globally Synchronized
Updates to the register are delayed until the next time the
counter is 0 after a synchronous update has been requested
through the PWMCTL register.
0x3
0x0RWDBFALLUPD15:14
1709June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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