Register 9: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 570
Register 10: Hibernation RTC Sub Seconds (HIBRTCSS), offset 0x028 ............................................... 571
Register 11: Hibernation IO Configuration (HIBIO), offset 0x02C .......................................................... 572
Register 12: Hibernation Data (HIBDATA), offset 0x030-0x06F ............................................................ 574
Register 13: Hibernation Calendar Control (HIBCALCTL), offset 0x300 ................................................ 575
Register 14: Hibernation Calendar 0 (HIBCAL0), offset 0x310 ............................................................. 576
Register 15: Hibernation Calendar 1 (HIBCAL1), offset 0x314 ............................................................. 578
Register 16: Hibernation Calendar Load 0 (HIBCALLD0), offset 0x320 ................................................. 580
Register 17: Hibernation Calendar Load (HIBCALLD1), offset 0x324 ................................................... 582
Register 18: Hibernation Calendar Match 0 (HIBCALM0), offset 0x330 ................................................ 583
Register 19: Hibernation Calendar Match 1 (HIBCALM1), offset 0x334 ................................................ 585
Register 20: Hibernation Lock (HIBLOCK), offset 0x360 ...................................................................... 586
Register 21: HIB Tamper Control (HIBTPCTL), offset 0x400 ................................................................ 587
Register 22: HIB Tamper Status (HIBTPSTAT), offset 0x404 ................................................................ 589
Register 23: HIB Tamper I/O Control (HIBTPIO), offset 0x410 ............................................................. 591
Register 24: HIB Tamper Log 0 (HIBTPLOG0), offset 0x4E0 ................................................................ 595
Register 25: HIB Tamper Log 2 (HIBTPLOG2), offset 0x4E8 ................................................................ 595
Register 26: HIB Tamper Log 4 (HIBTPLOG4), offset 0x4F0 ................................................................ 595
Register 27: HIB Tamper Log 6 (HIBTPLOG6), offset 0x4F8 ................................................................ 595
Register 28: HIB Tamper Log 1 (HIBTPLOG1), offset 0x4E4 ................................................................ 596
Register 29: HIB Tamper Log 3 (HIBTPLOG3), offset 0x4EC ............................................................... 596
Register 30: HIB Tamper Log 5 (HIBTPLOG5), offset 0x4F4 ................................................................ 596
Register 31: HIB Tamper Log 7 (HIBTPLOG7), offset 0x4FC ............................................................... 596
Register 32: Hibernation Peripheral Properties (HIBPP) , offset 0xFC0 ................................................. 598
Register 33: Hibernation Clock Control (HIBCC), offset 0xFC8 ............................................................ 599
Internal Memory ........................................................................................................................... 600
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 625
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 626
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 627
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 630
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 633
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 635
Register 7: Flash Memory Control 2 (FMC2), offset 0x020 ................................................................. 638
Register 8: Flash Write Buffer Valid (FWBVAL), offset 0x030 ............................................................. 639
Register 9: Flash Program/Erase Key (FLPEKEY), offset 0x03C ........................................................ 640
Register 10: Flash Write Buffer n (FWBn), offset 0x100 - 0x17C .......................................................... 641
Register 11: Flash Peripheral Properties (FLASHPP), offset 0xFC0 ..................................................... 642
Register 12: SRAM Size (SSIZE), offset 0xFC4 .................................................................................. 644
Register 13: Flash Configuration Register (FLASHCONF), offset 0xFC8 .............................................. 645
Register 14: ROM Third-Party Software (ROMSWMAP), offset 0xFCC ................................................. 647
Register 15: Flash DMA Address Size (FLASHDMASZ), offset 0xFD0 ................................................. 649
Register 16: Flash DMA Starting Address (FLASHDMAST), offset 0xFD4 ............................................ 650
Register 17: EEPROM Size Information (EESIZE), offset 0x000 .......................................................... 651
Register 18: EEPROM Current Block (EEBLOCK), offset 0x004 .......................................................... 652
Register 19: EEPROM Current Offset (EEOFFSET), offset 0x008 ........................................................ 653
Register 20: EEPROM Read-Write (EERDWR), offset 0x010 .............................................................. 654
Register 21: EEPROM Read-Write with Increment (EERDWRINC), offset 0x014 .................................. 655
Register 22: EEPROM Done Status (EEDONE), offset 0x018 .............................................................. 656
June 18, 201430
Texas Instruments-Production Data
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