Texas Instruments TM4C1294NCPDT - Page 32

Register 71: User Register 2 (USER_REG2), offset 0x1E8 .................................................................. 677
Register 72: User Register 3 (USER_REG3), offset 0x1EC ................................................................. 677
Micro Direct Memory Access (μDMA) ........................................................................................ 678
Register 1: DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000 ...................... 703
Register 2: DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004 ................ 704
Register 3: DMA Channel Control Word (DMACHCTL), offset 0x008 .................................................. 705
Register 4: DMA Status (DMASTAT), offset 0x000 ............................................................................ 710
Register 5: DMA Configuration (DMACFG), offset 0x004 ................................................................... 712
Register 6: DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008 .................................. 713
Register 7: DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C .................... 714
Register 8: DMA Channel Wait-on-Request Status (DMAWAITSTAT), offset 0x010 ............................. 715
Register 9: DMA Channel Software Request (DMASWREQ), offset 0x014 ......................................... 716
Register 10: DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018 .................................... 717
Register 11: DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C ................................. 718
Register 12: DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 .............................. 719
Register 13: DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 ........................... 720
Register 14: DMA Channel Enable Set (DMAENASET), offset 0x028 ................................................... 721
Register 15: DMA Channel Enable Clear (DMAENACLR), offset 0x02C ............................................... 722
Register 16: DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030 .................................... 723
Register 17: DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 ................................. 724
Register 18: DMA Channel Priority Set (DMAPRIOSET), offset 0x038 ................................................. 725
Register 19: DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C .............................................. 726
Register 20: DMA Bus Error Clear (DMAERRCLR), offset 0x04C ........................................................ 727
Register 21: DMA Channel Assignment (DMACHASGN), offset 0x500 ................................................. 728
Register 22: DMA Channel Map Select 0 (DMACHMAP0), offset 0x510 ............................................... 729
Register 23: DMA Channel Map Select 1 (DMACHMAP1), offset 0x514 ............................................... 730
Register 24: DMA Channel Map Select 2 (DMACHMAP2), offset 0x518 ............................................... 731
Register 25: DMA Channel Map Select 3 (DMACHMAP3), offset 0x51C .............................................. 732
Register 26: DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 ......................................... 733
Register 27: DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4 ......................................... 734
Register 28: DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8 ......................................... 735
Register 29: DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC ........................................ 736
Register 30: DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0 ......................................... 737
Register 31: DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0 ........................................... 738
Register 32: DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4 ........................................... 739
Register 33: DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8 ........................................... 740
Register 34: DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC ........................................... 741
General-Purpose Input/Outputs (GPIOs) ................................................................................... 742
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 759
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 760
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 761
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 762
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 763
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 764
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 765
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 767
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 769
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 770
June 18, 201432
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