5.2.4 Power Control ............................................................................................................. 229
5.2.5 Clock Control .............................................................................................................. 230
5.2.6 System Control ........................................................................................................... 239
5.3 Initialization and Configuration ..................................................................................... 246
5.4 Register Map .............................................................................................................. 247
5.5 System Control Register Descriptions (System Control Offset) ....................................... 254
6 Processor Support and Exception Module ........................................................ 523
6.1 Functional Description ................................................................................................. 523
6.2 Register Map .............................................................................................................. 523
6.3 Register Descriptions .................................................................................................. 523
7 Hibernation Module .............................................................................................. 531
7.1 Block Diagram ............................................................................................................ 533
7.2 Signal Description ....................................................................................................... 533
7.3 Functional Description ................................................................................................. 534
7.3.1 Register Access Timing ............................................................................................... 535
7.3.2 Hibernation Clock Source ............................................................................................ 535
7.3.3 System Implementation ............................................................................................... 538
7.3.4 Battery Management ................................................................................................... 539
7.3.5 Real-Time Clock .......................................................................................................... 539
7.3.6 Tamper ....................................................................................................................... 542
7.3.7 Battery-Backed Memory .............................................................................................. 545
7.3.8 Power Control Using HIB ............................................................................................. 545
7.3.9 Power Control Using VDD3ON Mode ........................................................................... 546
7.3.10 Initiating Hibernate ...................................................................................................... 546
7.3.11 Waking from Hibernate ................................................................................................ 546
7.3.12 Arbitrary Power Removal ............................................................................................. 547
7.3.13 Interrupts and Status ................................................................................................... 548
7.4 Initialization and Configuration ..................................................................................... 548
7.4.1 Initialization ................................................................................................................. 548
7.4.2 RTC Match Functionality (No Hibernation) .................................................................... 549
7.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 549
7.4.4 External Wake-Up from Hibernation .............................................................................. 550
7.4.5 RTC or External Wake-Up from Hibernation .................................................................. 551
7.4.6 Tamper Initialization ..................................................................................................... 551
7.5 Register Map .............................................................................................................. 551
7.6 Register Descriptions .................................................................................................. 553
8 Internal Memory ................................................................................................... 600
8.1 Block Diagram ............................................................................................................ 600
8.2 Functional Description ................................................................................................. 602
8.2.1 SRAM ........................................................................................................................ 602
8.2.2 ROM .......................................................................................................................... 602
8.2.3 Flash Memory ............................................................................................................. 604
8.2.4 EEPROM .................................................................................................................... 615
8.2.5 Bus Matrix Memory Accesses ...................................................................................... 621
8.3 Register Map .............................................................................................................. 621
8.4 Internal Memory Register Descriptions (Internal Memory Control Offset) ......................... 624
8.5 EEPROM Register Descriptions (EEPROM Offset) ........................................................ 650
8.6 Memory Register Descriptions (System Control Offset) .................................................. 667
5June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller