Texas Instruments TM4C1294NCPDT - Page 563

DescriptionResetTypeNameBit/Field
Pad I/O Wake-Up Interrupt Mask
DescriptionValue
The PADIOWK interrupt is suppressed and not sent to the
interrupt controller.
0
An interrupt is sent to the interrupt controller when the PADIOWK
bit in the HIBRIS register is set.
1
0RWPADIOWK5
External Write Complete/Capable Interrupt Mask
DescriptionValue
The WC interrupt is suppressed and not sent to the interrupt
controller.
0
An interrupt is sent to the interrupt controller when the WC bit in
the HIBRIS register is set.
1
0RWWC4
External Wake-Up Interrupt Mask
DescriptionValue
The EXTW interrupt is suppressed and not sent to the interrupt
controller.
0
An interrupt is sent to the interrupt controller when the EXTW bit
in the HIBRIS register is set.
1
0RWEXTW3
Low Battery Voltage Interrupt Mask
DescriptionValue
The LOWBAT interrupt is suppressed and not sent to the interrupt
controller.
0
An interrupt is sent to the interrupt controller when the LOWBAT
bit in the HIBRIS register is set.
1
0RWLOWBAT2
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved1
RTC Alert 0 Interrupt Mask
DescriptionValue
The RTCALT0 interrupt is suppressed and not sent to the
interrupt controller.
0
An interrupt is sent to the interrupt controller when the RTCALT0
bit in the HIBRIS register is set.
1
0RWRTCALT00
563June 18, 2014
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TM4C1294NCPDT Microcontroller