Texas Instruments TM4C1294NCPDT - Page 567

DescriptionResetTypeNameBit/Field
Write Complete/Capable Masked Interrupt Status
DescriptionValue
The WRC bit has not been set or the interrupt is masked.0
An unmasked interrupt was signaled due to the WRC bit being
set.
1
This bit is cleared by writing a 1 to the WC bit in the HIBIC register.
0ROWC4
External Wake-Up Masked Interrupt Status
DescriptionValue
An external wake-up interrupt has not occurred or is masked.0
An unmasked interrupt was signaled due to a WAKE pin
assertion.
1
This bit is cleared by writing a 1 to the EXTW bit in the HIBIC register.
0ROEXTW3
Low Battery Voltage Masked Interrupt Status
DescriptionValue
A low-battery voltage interrupt has not occurred or is masked.0
An unmasked interrupt was signaled due to a low-battery voltage
condition.
1
This bit is cleared by writing a 1 to the LOWBAT bit in the HIBIC register.
0ROLOWBAT2
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved1
RTC Alert 0 Masked Interrupt Status
Note: The MIS may apply to either the RTC or calendar block
depending on which is enabled.
DescriptionValue
An RTC or calendar match interrupt has not occurred or is
masked.
0
An unmasked interrupt was signaled due to an RTC or calendar
match.
1
This bit is cleared by writing a 1 to the RTCALT0 bit in the HIBIC register.
0RORTCALT00
567June 18, 2014
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TM4C1294NCPDT Microcontroller