Texas Instruments TM4C1294NCPDT - Page 593

DescriptionResetTypeNameBit/Field
TMPR1 Glitch Filtering
DescriptionValue
A trigger match level is ignored until the TMPR1 signal is stable
for two hibernate clocks.
0
A trigger match level is ignored until the TMPR1 signal is stable
for 3,071 Hibernate Clocks (93.7ms using 32.768 kHz).
1
0RWGFLTR111
TMPR1 Internal Weak Pull-up Enable
DescriptionValue
Pull-up disabled0
Pull-up enabled1
0RWPUEN110
TMPR1 Trigger Level
DescriptionValue
Trigger on level low0
Trigger on level high1
0RWLEV19
TMPR1Enable
DescriptionValue
Detect disabled0
Detect enabled1
0RWEN18
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved7:4
TMPR0 Glitch Filtering
DescriptionValue
A trigger match level is ignored until the TMPR0 signal is stable
for two hibernate clocks.
0
A trigger match level is ignored until the TMPR0 signal is stable
for 3,071 Hibernate Clocks (93.7ms using 32.768 kHz).
1
0RWGFLTR03
TMPR0 Internal Weak Pull-up Enable
DescriptionValue
Pull-up disabled0
Pull-up enabled1
0RWPUEN02
593June 18, 2014
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TM4C1294NCPDT Microcontroller