DescriptionResetTypeNameBit/Field
Clock Gated
DescriptionValue
The EPI clock is free running.0
The EPI clock is output only when there is data to write or read
(current transaction); otherwise the EPI clock is held low.
1
CLKGATE is ignored if CLKPIN is 0 or if the COUNT0 field in the EPIBAUD
register is cleared.
0RWCLKGATE30
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved29:27
50/50 Frame
DescriptionValue
The FRAME signal is output as a single pulse, and then held
low for the count.
0
The FRAME signal is output as 50/50 duty cycle using count
(see FRMCNT).
1
0RWFRM5026
Frame Count
This field specifies the size of the frame in EPI clocks. The frame counter
is used to determine the frame size. The count is FRMCNT+1. So, a
FRMCNT of 0 forms a pure transaction valid signal (held high during
transactions, low otherwise).
A FRMCNT of 0 with FRM50 set inverts the FRAME signal on each
transaction. A FRMCNT of 1 means the FRAME signal is inverted every
other transaction; a value of 15 means every sixteenth transaction.
If FRM50 is set, the frame is held high for FRMCNT+1 transactions, then
held low for that many transactions, and so on.
If FRM50 is clear, the frame is pulsed high for one EPI clock and then
low for FRMCNT EPI clocks.
0x0RWFRMCNT25:22
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved21:20
2-Cycle Writes
DescriptionValue
Data is output on the same EPI clock cycle as the address.
EPI clock begins toggling one cycle before the WR strobe goes
High.
0
Writes are two EPI clock cycles long, with address on one EPI
clock cycle (with the WR strobe asserted) and data written on
the following EPI clock cycle (with WR strobe deasserted). The
next address (if any) is in the cycle following.
If the WR2CYC bit is set, the EPI clock begins toggling when the
WR strobe goes High.
1
When this bit is set, then the RW bit is forced to be set.
0RWWR2CYC19
877June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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