DescriptionResetTypeNameBit/Field
Chip Select Configuration
This field controls the chip select options, including an ALE format, a
single chip select, two chip selects, and an ALE combined with two chip
selects. These bits are also used in combination with the CSCFGEXT bit
for further configurations, including quad- chip select.
DescriptionValue
ALE Configuration
EPI0S30 is used as an address latch (ALE). When using this
mode, the address and data should be muxed (HB16MODE field
in the EPIHB16CFG register should be configured to 0x0). If
needed, the address can be latched by external logic.
0x0
CSn Configuration
EPI0S30 is used as a Chip Select (CSn). When using this mode,
the address and data should not be muxed (MODE field in the
EPIHB16CFG register should be configured to 0x1). In this
mode, the WR signal (EPI0S29) and the RD signal (EPI0S28)
are used to latch the address when CSn is low.
0x1
Dual CSn Configuration
EPI0S30 is used as CS0n and EPI0S27 is used as CS1n.
Whether CS0n or CS1n is asserted is determined by the most
significant address bit for a respective external address map.
This configuration can be used for a RAM bank split between
2 devices as well as when using both an external RAM and an
external peripheral.
0x2
ALE with Dual CSn Configuration
EPI0S30 is used as address latch (ALE), EPI0S27 is used as
CS1n, and EPI0S26 is used as CS0n. Whether CS0n or CS1n
is asserted is determined by the most significant address bit for
a respective external address map.
0x3
0x0RWCSCFG25:24
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved23:22
CS1n WRITE Strobe Polarity
This field is used if CSBAUD bit of the EPIHB16CFG2 register is enabled.
DescriptionValue
The WRITE strobe for CS1n accesses is WRn (active Low).0
The WRITE strobe for CS1n accesses is WR (active High).1
0RWWRHIGH21
CS1n READ Strobe Polarity
This field is used if CSBAUD bit of the EPIHB16CFG2 register is enabled.
DescriptionValue
The READ strobe for CS1n accesses is RDn (active Low).0
The READ strobe for CS1n accesses is RD (active High).1
0RWRDHIGH20
June 18, 2014888
Texas Instruments-Production Data
External Peripheral Interface (EPI)
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