DescriptionResetTypeNameBit/Field
CS1n Write Wait States
This field adds wait states to the data phase of CS1n accesses (the
address phase is not affected).
The effect is to delay the rising edge of WRn (or the falling edge of WR).
Each wait state encoding adds 2 EPI clock cycles to the access time.
The WRWSM bit in the EPIHB16TIME2 register can decrease the number
of wait states by 1 EPI clock cycle for greater granularity.
This field is used if the CSBAUD bit is enabled in the EPIHB16CFG2
register. This field is used in conjunction with the EPIBAUD register and
is not applicable in BURST mode.
DescriptionValue
Active WRn is 2 EPI clocks0x0
Active WRn is 4 EPI clocks.0x1
Active WRn is 6 EPI clocks0x2
Active WRn is 8 EPI clocks0x3
0x0RWWRWS7:6
CS1n Read Wait States
This field adds wait states to the data phase of CS1n accesses (the
address phase is not affected).
The effect is to delay the rising edge of RDn/Oen (or the falling edge of
RD). Each wait state encoding adds 2 EPI clock cycles to the access
time. The RDWSM bit in the EPIHB16TIME2 register can decrease the
number of states by 1 EPI clock cycle for greater granularity.
This field is used if the CSBAUD bit is enabled in the EPIHB16CFG2
register. This field is used in conjunction with the EPIBAUD register and
is not applicable in BURST mode.
DescriptionValue
Active RDn is 2 EPI clocks0x0
Active RDn is 4 EPI clocks0x1
Active RDn is 6 EPI clocks0x2
Active RDn is 8 EPI clocks0x3
0x0RWRDWS5:4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved3:2
June 18, 2014890
Texas Instruments-Production Data
External Peripheral Interface (EPI)
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