DescriptionResetTypeNameBit/Field
CS2n PSRAM Configuration Register Write
Used for PSRAM configuration registers.
With WRCRE set, the next transaction by the EPI is a write of the CR bit
field in the EPIHBPSRAM register to the configuration register (CR) of
the PSRAM. The WRCRE bit self clears once the write-enabled CRE
access is complete.
DescriptionValue
No Action.0
Start CRE write transaction for CS2n.1
0RWWRCRE18
CS2n PSRAM Configuration Register Read
Used for PSRAM configuration registers.
With the RDCRE set, the next access is a read of the PSRAM's
Configuration Register (CR). This bit self clears once the CRE access
is complete. The address for the CRE access is located at
EPIHBPSRAM[19:18]. The read data is returned on
EPIHBPSRAM[15:0].
DescriptionValue
No Action.0
Start CRE read transaction for CS2n.1
0RWRDCRE17
CS2n Burst Mode
Burst mode must be used with an ALE, which is configured by
programming the CSCFG and CSCFGEXT fields in the EPIHB16CFG2
register. Burst mode must be used in ADMUX, which is set by the MODE
field in EPIHB16CFG3.
Note: Burst mode is optimized for word-length accesses.
DescriptionValue
Burst mode is disabled.0
Burst mode is enabled for CS2n.1
0RWBURST16
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved15:8
919June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
To Next Page
Loading...
Need help?
General
