DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved15:14
CS3n Inter-transfer Capture Width
Controls the delay between Host-Bus transfers.
DescriptionValue
Reserved0x0
1 EPI clock.0x1
2 EPI clock.0x2
Reserved0x3
0x2RWCAPWIDTH13:12
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved11:5
CS3n Write Wait State Minus One
This bit is used with the WRWS field in EPIHB16CFG4. This field is not
applicable in BURST mode.
DescriptionValue
No change in the number of wait state clock cycles programmed
in the in WRWS field in EPIHB16CFG4 register.
0
Wait state value is now:
WRWS - 1
WRWS field is programmed in EPIHB16CFG4.
1
0RWWRWSM4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved3:1
CS3n Read Wait State Minus One
This field is used with RDWS field in EPIHB16CFG4. This bit is not
applicable in BURST mode.
DescriptionValue
No change in the number of wait state clock cycles programmed
in the RDWS field of EPIHB16CFG4.
0
Wait state value is now:
RDWS - 1
RDWS field is programmed in EPIHB16CFG4.
1
0RWRDWSM0
June 18, 2014944
Texas Instruments-Production Data
External Peripheral Interface (EPI)
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