DescriptionResetTypeNameBit/Field
One-shot/Periodic Interrupt Disable
DescriptionValue
Time-out interrupt functions as normal.0
Time-out interrupt are disabled.1
Note: Setting the TACINTD bit in the GPTMTAMR register
does not have an effect on the µDMA or ADC interrupt
time-out event trigger assertions. If the TATODMAEN
bit is set in the GPTMDMAEV register or the
TATOADCEN bit is set in the GPTMADCEV register,
a µDMA or ADC time-out trigger is sent to the µDMA
or ADC, respectively, even if the TACINTD bit is set.
0RWTACINTD12
GPTM Timer A PWM Legacy Operation
DescriptionValue
Legacy operation with CCP pin driven Low when the
GPTMTAILR is reloaded after the timer reaches 0.
0
CCP is driven High when the GPTMTAILR is reloaded after the
timer reaches 0.
1
This bit is only valid in PWM mode.
0RWTAPLO11
GPTM Timer A Match Register Update
DescriptionValue
Update the GPTMTAMATCHR register and the GPTMTAPR
register, if used, on the next cycle.
0
Update the GPTMTAMATCHR register and the GPTMTAPR
register, if used, on the next timeout.
1
If the timer is disabled (TAEN is clear) when this bit is set,
GPTMTAMATCHR and GPTMTAPR are updated when the timer is
enabled. If the timer is stalled (TASTALL is set), GPTMTAMATCHR and
GPTMTAPR are updated according to the configuration of this bit.
0RWTAMRSU10
GPTM Timer A PWM Interrupt Enable
This bit enables interrupts in PWM mode on rising, falling, or both edges
of the CCP output, as defined by the TAEVENT field in the GPTMCTL
register.
In addition, when this bit is set and a capture event occurs, Timer A
automatically generates triggers to the ADC and DMA if the trigger
capability is enabled by setting the TAOTE bit in the GPTMCTL register
and the CAEDMAEN bit in the GPTMDMAEV register, respectively.
DescriptionValue
Capture event interrupt is disabled.0
Capture event interrupt is enabled.1
This bit is only valid in PWM mode.
0RWTAPWMIE9
June 18, 2014978
Texas Instruments-Production Data
General-Purpose Timers
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