DescriptionResetTypeNameBit/Field
Digital Comparator Interrupt Status on SS1
DescriptionValue
No interrupt has occurred or the interrupt is masked.0
Both the INRDC bit in the ADCRIS register and the DCONSS1
bit in the ADCIM register are set, providing a level-based
interrupt to the interrupt controller.
1
This bit is cleared by writing a 1 to it. Clearing this bit also clears the
INRDC bit in the ADCRIS register.
0RODCINSS117
Digital Comparator Interrupt Status on SS0
DescriptionValue
No interrupt has occurred or the interrupt is masked.0
Both the INRDC bit in the ADCRIS register and the DCONSS0
bit in the ADCIM register are set, providing a level-based
interrupt to the interrupt controller.
1
This bit is cleared by writing a 1 to it. Clearing this bit also clears the
INRDC bit in the ADCRIS register.
0RODCINSS016
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved15:12
SS3 DMA Interrupt Status and Clear
DescriptionValue
No interrupt has occurred or the interrupt is masked.0
Both the DMAINR3 bit in the ADCRIS register and the DMAMASK3
bit in the ADCIM register are set, providing a level-based
interrupt to the interrupt controller.
1
This bit is cleared by writing a 1. Clearing this bit also clears the
DMAINR3 bit in the ADCRIS register.
0RW1CDMAIN311
SS2 DMA Interrupt Status and Clear
DescriptionValue
No interrupt has occurred or the interrupt is masked.0
Both the DMAINR2 bit in the ADCRIS register and the DMAMASK2
bit in the ADCIM register are set, providing a level-based
interrupt to the interrupt controller.
1
This bit is cleared by writing a 1. Clearing this bit also clears the
DMAINR2 bit in the ADCRIS register.
0RW1CDMAIN210
June 18, 20141086
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
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