Texas Instruments TM4C1294NCPDT User Manual

DescriptionResetTypeNameBit/Field
SS1 DMA Interrupt Status and Clear
DescriptionValue
No interrupt has occurred or the interrupt is masked.0
Both the DMAINR1 bit in the ADCRIS register and the DMAMASK1
bit in the ADCIM register are set, providing a level-based
interrupt to the interrupt controller.
1
This bit is cleared by writing a 1. Clearing this bit also clears the
DMAINR1 bit in the ADCRIS register.
0RW1CDMAIN19
SS0 DMA Interrupt Status and Clear
DescriptionValue
No interrupt has occurred or the interrupt is masked.0
Both the DMAINR0 bit in the ADCRIS register and the DMAMASK0
bit in the ADCIM register are set, providing a level-based
interrupt to the interrupt controller.
1
This bit is cleared by writing a 1. Clearing this bit also clears the
DMAINR0 bit in the ADCRIS register.
0RW1CDMAIN08
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved7:4
SS3 Interrupt Status and Clear
DescriptionValue
No interrupt has occurred or the interrupt is masked.0
Both the INR3 bit in the ADCRIS register and the MASK3 bit in
the ADCIM register are set, providing a level-based interrupt to
the interrupt controller.
1
This bit is cleared by writing a 1. Clearing this bit also clears the INR3
bit in the ADCRIS register.
0RW1CIN33
SS2 Interrupt Status and Clear
DescriptionValue
No interrupt has occurred or the interrupt is masked.0
Both the INR2 bit in the ADCRIS register and the MASK2 bit in
the ADCIM register are set, providing a level-based interrupt to
the interrupt controller.
1
This bit is cleared by writing a 1. Clearing this bit also clears the INR2
bit in the ADCRIS register.
0RW1CIN22
1087June 18, 2014
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TM4C1294NCPDT Microcontroller

Texas Instruments TM4C1294NCPDT Specifications

General

Brand	Texas Instruments
Model	TM4C1294NCPDT
Category	Microcontrollers
Language	English