DescriptionResetTypeNameBit/Field
UART Loop Back Enable
DescriptionValue
Normal operation.0
The UnTx path is fed through the UnRx path.1
0RWLBE7
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved6
High-Speed Enable
DescriptionValue
The UART is clocked using the system clock divided by 16.0
The UART is clocked using the system clock divided by 8.1
Note: System clock used is also dependent on the baud-rate divisor
configuration (see page 1184) and page 1185).
The state of this bit has no effect on clock generation in ISO
7816 smart card mode (the SMART bit is set).
0RWHSE5
End of Transmission
This bit determines the behavior of the TXRIS bit in the UARTRIS
register.
DescriptionValue
The TXRIS bit is set when the transmit FIFO condition specified
in UARTIFLS is met.
0
The TXRIS bit is set only after all transmitted data, including
stop bits, have cleared the serializer.
1
0RWEOT4
ISO 7816 Smart Card Support
DescriptionValue
Normal operation.0
The UART operates in Smart Card mode.1
The application must ensure that it sets 8-bit word length (WLEN set to
0x3) and even parity (PEN set to 1, EPS set to 1, SPS set to 0) in
UARTLCRH when using ISO 7816 mode.
In this mode, the value of the STP2 bit in UARTLCRH is ignored and
the number of stop bits is forced to 2. Note that the UART does not
support automatic retransmission on parity errors. If a parity error is
detected on transmission, all further transmit operations are aborted
and software must handle retransmission of the affected byte or
message.
0RWSMART3
June 18, 20141190
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
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