Texas Instruments TM4C1294NCPDT User Manual

List of Figures
Figure 1-1. Tiva
™
TM4C1294NCPDT Microcontroller High-Level Block Diagram ....................... 54
Figure 2-1. CPU Block Diagram ............................................................................................. 82
Figure 2-2. TPIU Block Diagram ............................................................................................ 83
Figure 2-3. Cortex-M4F Register Set ...................................................................................... 86
Figure 2-4. Bit-Band Mapping .............................................................................................. 111
Figure 2-5. Data Storage ..................................................................................................... 112
Figure 2-6. Vector Table ...................................................................................................... 119
Figure 2-7. Exception Stack Frame ...................................................................................... 122
Figure 3-1. SRD Use Example ............................................................................................. 140
Figure 3-2. FPU Register Bank ............................................................................................ 143
Figure 4-1. JTAG Module Block Diagram .............................................................................. 208
Figure 4-2. Test Access Port State Machine ......................................................................... 212
Figure 4-3. IDCODE Register Format ................................................................................... 218
Figure 4-4. BYPASS Register Format ................................................................................... 218
Figure 4-5. Boundary Scan Register Format ......................................................................... 218
Figure 5-1. Basic RST Configuration .................................................................................... 224
Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 224
Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 224
Figure 5-4. Power Architecture ............................................................................................ 229
Figure 5-5. Main Clock Tree ................................................................................................ 233
Figure 5-6. Module Clock Selection ...................................................................................... 242
Figure 7-1. Hibernation Module Block Diagram ..................................................................... 533
Figure 7-2. Using a Crystal as the Hibernation Clock Source with a Single Battery Source ...... 537
Figure 7-3. Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON
Mode ................................................................................................................ 537
Figure 7-4. Using a Regulator for Both V
DD
and V
BAT
............................................................ 538
Figure 7-5. Counter Behavior with a TRIM Value of 0x8002 ................................................... 542
Figure 7-6. Counter Behavior with a TRIM Value of 0x7FFC .................................................. 542
Figure 7-7. Tamper Block Diagram ....................................................................................... 542
Figure 7-8. Tamper Pad with Glitch Filtering ......................................................................... 543
Figure 8-1. Internal Memory Block Diagram .......................................................................... 601
Figure 8-2. Flash Memory Configuration ............................................................................... 605
Figure 8-3. Single 256-Bit Prefetch Buffer Set ....................................................................... 606
Figure 8-4. Four 256-Bit Prefetch Buffer Configuration .......................................................... 606
Figure 8-5. Single Cycle Access, 0 Wait States ..................................................................... 607
Figure 8-6. Prefetch Fills from Flash ..................................................................................... 608
Figure 8-7. Mirror Mode Function ......................................................................................... 609
Figure 9-1. μDMA Block Diagram ......................................................................................... 679
Figure 9-2. Example of Ping-Pong μDMA Transaction ........................................................... 686
Figure 9-3. Memory Scatter-Gather, Setup and Configuration ................................................ 688
Figure 9-4. Memory Scatter-Gather, μDMA Copy Sequence .................................................. 689
Figure 9-5. Peripheral Scatter-Gather, Setup and Configuration ............................................. 691
Figure 9-6. Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 692
Figure 10-1. Digital I/O Pads ................................................................................................. 747
Figure 10-2. Analog/Digital I/O Pads ...................................................................................... 748
Figure 10-3. GPIODATA Write Example ................................................................................. 749
June 18, 201412
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Table of Contents

Texas Instruments TM4C1294NCPDT Specifications

General

Brand	Texas Instruments
Model	TM4C1294NCPDT
Category	Microcontrollers
Language	English