Texas Instruments TM4C1294NCPDT User Manual

Figure 10-4. GPIODATA Read Example ................................................................................. 749
Figure 11-1. EPI Block Diagram ............................................................................................. 817
Figure 11-2. SDRAM Non-Blocking Read Cycle ...................................................................... 824
Figure 11-3. SDRAM Normal Read Cycle ............................................................................... 825
Figure 11-4. SDRAM Write Cycle ........................................................................................... 826
Figure 11-5. iRDY Access Stalls, IRDYDLY==01, 10, 11 .......................................................... 836
Figure 11-6. iRDY Signal Connection ..................................................................................... 836
Figure 11-7. PSRAM Burst Read ........................................................................................... 839
Figure 11-8. PSRAM Burst Write ........................................................................................... 839
Figure 11-9. Read Delay During Refresh Event ...................................................................... 840
Figure 11-10. Write Delay During Refresh Event ....................................................................... 841
Figure 11-11. Example Schematic for Muxed Host-Bus 16 Mode ............................................... 842
Figure 11-12. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 845
Figure 11-13. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 845
Figure 11-14. Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH
= 0, RDHIGH = 0 ............................................................................................... 846
Figure 11-15. Host-Bus Write Cycle with Multiplexed Address and Data and ALE with Dual or
Quad CSn ......................................................................................................... 846
Figure 11-16. Continuous Read Mode Accesses ...................................................................... 846
Figure 11-17. Write Followed by Read to External FIFO ............................................................ 847
Figure 11-18. Two-Entry FIFO ................................................................................................. 847
Figure 11-19. Single-Cycle Single Write Access, FRM50=0, FRMCNT=0, WR2CYC=0 ............... 850
Figure 11-20. Two-Cycle Read, Write Accesses, FRM50=0, FRMCNT=0, WR2CYC=1 ............... 851
Figure 11-21. Read Accesses, FRM50=0, FRMCNT=0 ............................................................. 851
Figure 11-22. FRAME Signal Operation, FRM50=0 and FRMCNT=0 ......................................... 852
Figure 11-23. FRAME Signal Operation, FRM50=0 and FRMCNT=1 ......................................... 852
Figure 11-24. FRAME Signal Operation, FRM50=0 and FRMCNT=2 ......................................... 852
Figure 11-25. FRAME Signal Operation, FRM50=1 and FRMCNT=0 ......................................... 852
Figure 11-26. FRAME Signal Operation, FRM50=1 and FRMCNT=1 ......................................... 853
Figure 11-27. FRAME Signal Operation, FRM50=1 and FRMCNT=2 ......................................... 853
Figure 11-28. EPI Clock Operation, CLKGATE=1, WR2CYC=0 ................................................. 853
Figure 11-29. EPI Clock Operation, CLKGATE=1, WR2CYC=1 ................................................. 854
Figure 13-1. GPTM Module Block Diagram ............................................................................ 956
Figure 13-2. Input Edge-Count Mode Example, Counting Down ............................................... 964
Figure 13-3. 16-Bit Input Edge-Time Mode Example ............................................................... 965
Figure 13-4. 16-Bit PWM Mode Example ................................................................................ 967
Figure 13-5. CCP Output, GPTMTnMATCHR > GPTMTnILR ................................................... 967
Figure 13-6. CCP Output, GPTMTnMATCHR = GPTMTnILR ................................................... 968
Figure 13-7. CCP Output, GPTMTnILR > GPTMTnMATCHR ................................................... 968
Figure 13-8. Timer Daisy Chain ............................................................................................. 969
Figure 14-1. WDT Module Block Diagram ............................................................................. 1029
Figure 15-1. Implementation of Two ADC Blocks .................................................................. 1054
Figure 15-2. ADC Module Block Diagram ............................................................................. 1055
Figure 15-3. ADC Sample Phases ....................................................................................... 1060
Figure 15-4. Doubling the ADC Sample Rate ........................................................................ 1060
Figure 15-5. Skewed Sampling ............................................................................................ 1061
Figure 15-6. Sample Averaging Example .............................................................................. 1063
Figure 15-7. ADC Input Equivalency .................................................................................... 1064
13June 18, 2014
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TM4C1294NCPDT Microcontroller

Texas Instruments TM4C1294NCPDT Specifications

General

Brand	Texas Instruments
Model	TM4C1294NCPDT
Category	Microcontrollers
Language	English