Texas Instruments TM4C1294NCPDT User Manual

Figure 15-8. ADC Voltage Reference ................................................................................... 1064
Figure 15-9. ADC Conversion Result ................................................................................... 1065
Figure 15-10. Differential Voltage Representation ................................................................... 1067
Figure 15-11. Internal Temperature Sensor Characteristic ....................................................... 1068
Figure 15-12. Low-Band Operation (CIC=0x0 and/or CTC=0x0) .............................................. 1070
Figure 15-13. Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ............................................... 1071
Figure 15-14. High-Band Operation (CIC=0x3 and/or CTC=0x3) .............................................. 1072
Figure 16-1. UART Module Block Diagram ........................................................................... 1162
Figure 16-2. UART Character Frame .................................................................................... 1165
Figure 16-3. IrDA Data Modulation ....................................................................................... 1167
Figure 17-1. QSSI Module with Advanced, Bi-SSI and Quad-SSI Support .............................. 1227
Figure 17-2. TI Synchronous Serial Frame Format (Single Transfer) ...................................... 1234
Figure 17-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................... 1235
Figure 17-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ........................ 1236
Figure 17-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 ................ 1236
Figure 17-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ....................................... 1237
Figure 17-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............. 1238
Figure 17-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ...... 1238
Figure 17-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ....................................... 1239
Figure 18-1. I
2
C Block Diagram ........................................................................................... 1276
Figure 18-2. I
2
C Bus Configuration ....................................................................................... 1278
Figure 18-3. START and STOP Conditions ........................................................................... 1279
Figure 18-4. Complete Data Transfer with a 7-Bit Address ..................................................... 1279
Figure 18-5. R/S Bit in First Byte .......................................................................................... 1280
Figure 18-6. Data Validity During Bit Transfer on the I
2
C Bus ................................................. 1280
Figure 18-7. High-Speed Data Format .................................................................................. 1286
Figure 18-8. Master Single TRANSMIT ................................................................................ 1290
Figure 18-9. Master Single RECEIVE ................................................................................... 1291
Figure 18-10. Master TRANSMIT of Multiple Data Bytes ......................................................... 1292
Figure 18-11. Master RECEIVE of Multiple Data Bytes ............................................................ 1293
Figure 18-12. Master RECEIVE with Repeated START after Master TRANSMIT ....................... 1294
Figure 18-13. Master TRANSMIT with Repeated START after Master RECEIVE ....................... 1295
Figure 18-14. Standard High Speed Mode Master Transmit ..................................................... 1296
Figure 18-15. Slave Command Sequence .............................................................................. 1297
Figure 19-1. CAN Controller Block Diagram .......................................................................... 1357
Figure 19-2. CAN Data/Remote Frame ................................................................................. 1358
Figure 19-3. Message Objects in a FIFO Buffer .................................................................... 1367
Figure 19-4. CAN Bit Time ................................................................................................... 1371
Figure 20-1. Ethernet MAC with Integrated PHY Interface ..................................................... 1408
Figure 20-2. Ethernet MAC and PHY Clock Structure ............................................................ 1410
Figure 20-3. Enhanced Transmit Descriptor Structure ........................................................... 1414
Figure 20-4. Enhanced Receive Descriptor Structure ............................................................ 1419
Figure 20-5. TX DMA Default Operation Using Descriptors .................................................... 1426
Figure 20-6. TX DMA OSF Mode Operation Using Descriptors .............................................. 1428
Figure 20-7. RX DMA Operation Flow .................................................................................. 1431
Figure 20-8. Networked Time Synchronization ...................................................................... 1441
Figure 20-9. System Time Update Using Fine Correction Method .......................................... 1443
June 18, 201414
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Table of Contents

Texas Instruments TM4C1294NCPDT Specifications

General

Brand	Texas Instruments
Model	TM4C1294NCPDT
Category	Microcontrollers
Language	English