Texas Instruments TM4C1294NCPDT User Manual

Figure 20-10. Propagation Delay Calculation in Clocks Supporting Peer-to-Peer Path
Correction ....................................................................................................... 1446
Figure 20-11. Wake-Up Frame Filter Register Bank ................................................................ 1454
Figure 20-12. Integrated PHY Diagram .................................................................................. 1458
Figure 20-13. Interface to Ethernet Jack ................................................................................. 1464
Figure 21-1. USB Module Block Diagram ............................................................................. 1645
Figure 22-1. Analog Comparator Module Block Diagram ....................................................... 1654
Figure 22-2. Structure of Comparator Unit ............................................................................ 1655
Figure 22-3. Comparator Internal Reference Structure .......................................................... 1656
Figure 23-1. PWM Module Diagram ..................................................................................... 1671
Figure 23-2. PWM Generator Block Diagram ........................................................................ 1671
Figure 23-3. PWM Count-Down Mode .................................................................................. 1674
Figure 23-4. PWM Count-Up/Down Mode ............................................................................. 1674
Figure 23-5. PWM Generation Example In Count-Up/Down Mode .......................................... 1675
Figure 23-6. PWM Dead-Band Generator ............................................................................. 1675
Figure 24-1. QEI Block Diagram .......................................................................................... 1749
Figure 24-2. QEI Input Signal Logic ...................................................................................... 1750
Figure 24-3. Quadrature Encoder and Velocity Predivider Operation ...................................... 1752
Figure 25-1. 128-Pin TQFP Package Pin Diagram ................................................................ 1771
Figure 27-1. Load Conditions ............................................................................................... 1823
Figure 27-2. JTAG Test Clock Input Timing ........................................................................... 1825
Figure 27-3. JTAG Test Access Port (TAP) Timing ................................................................ 1825
Figure 27-4. Power and Brown-Out Assertions vs V
DDA
Levels .............................................. 1827
Figure 27-5. Power and Brown-Out Assertions vs V
DD
Levels ................................................ 1828
Figure 27-6. POK Assertion vs V
DDC
................................................................................... 1829
Figure 27-7. POR-BOR V
DD
Glitch Response ....................................................................... 1829
Figure 27-8. POR-BOR V
DD
Droop Response ...................................................................... 1830
Figure 27-9. Digital Power-On Reset Timing ......................................................................... 1831
Figure 27-10. Brown-Out Reset Timing .................................................................................. 1832
Figure 27-11. External Reset Timing (RST) ............................................................................ 1832
Figure 27-12. Software Reset Timing ..................................................................................... 1832
Figure 27-13. Watchdog Reset Timing ................................................................................... 1832
Figure 27-14. MOSC Failure Reset Timing ............................................................................. 1833
Figure 27-15. Hibernation Module Timing ............................................................................... 1846
Figure 27-16. ESD Protection ................................................................................................ 1851
Figure 27-17. ESD Protection for Non-Power Pins (Except WAKE Signal) ................................ 1852
Figure 27-18. SDRAM Initialization and Load Mode Register Timing ........................................ 1854
Figure 27-19. SDRAM Read Timing ....................................................................................... 1854
Figure 27-20. SDRAM Write Timing ....................................................................................... 1855
Figure 27-21. Host-Bus 8/16 Asynchronous Mode Read Timing ............................................... 1856
Figure 27-22. Host-Bus 8/16 Asynchronous Mode Write Timing ............................................... 1856
Figure 27-23. Host-Bus 8/16 Mode Asynchronous Muxed Read Timing .................................... 1857
Figure 27-24. Host-Bus 8/16 Mode Asynchronous Muxed Write Timing .................................... 1857
Figure 27-25. General-Purpose Mode Read and Write Timing ................................................. 1858
Figure 27-26. PSRAM Single Burst Read ............................................................................... 1859
Figure 27-27. PSRAM Single Burst Write ............................................................................... 1860
Figure 27-28. ADC External Reference Filtering ..................................................................... 1866
Figure 27-29. ADC Input Equivalency .................................................................................... 1866
15June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller

Texas Instruments TM4C1294NCPDT Specifications

General

Brand	Texas Instruments
Model	TM4C1294NCPDT
Category	Microcontrollers
Language	English