DescriptionResetTypeNameBit/Field
UART Receive Time-Out Masked Interrupt Status
DescriptionValue
An interrupt has not occurred or is masked.0
An unmasked interrupt was signaled due to a receive time out.1
This bit is cleared by writing a 1 to the RTIC bit in the UARTICR register.
For receive timeout, the RTIM bit in the UARTIM register must be set
to see the RTMIS status.
0RORTMIS6
UART Transmit Masked Interrupt Status
DescriptionValue
An interrupt has not occurred or is masked.0
An unmasked interrupt was signaled due to passing through
the specified transmit FIFO level (if the EOT bit is clear) or due
to the transmission of the last data bit (if the EOT bit is set).
1
This bit is cleared by writing a 1 to the TXIC bit in the UARTICR register
or by writing data to the transmit FIFO until it becomes greater than the
trigger level, if the FIFO is enabled, or by writing a single byte if the FIFO
is disabled.
0ROTXMIS5
UART Receive Masked Interrupt Status
DescriptionValue
An interrupt has not occurred or is masked.0
An unmasked interrupt was signaled due to passing through
the specified receive FIFO level.
1
This bit is cleared by writing a 1 to the RXIC bit in the UARTICR register
or by reading data from the receive FIFO until it becomes less than the
trigger level, if the FIFO is enabled, or by reading a single byte if the
FIFO is disabled.
0RORXMIS4
UART Data Set Ready Modem Masked Interrupt Status
DescriptionValue
An interrupt has not occurred or is masked.0
An unmasked interrupt was signaled due to Data Set Ready.1
This bit is cleared by writing a 1 to the DSRIC bit in the UARTICR
register.
0RODSRMIS3
UART Data Carrier Detect Modem Masked Interrupt Status
DescriptionValue
An interrupt has not occurred or is masked.0
An unmasked interrupt was signaled due to Data Carrier Detect.1
This bit is cleared by writing a 1 to the DCDIC bit in the UARTICR
register.
0RODCDMIS2
June 18, 20141204
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
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