At reset, LED0 is initialized to display Link OK and LED1 and LED 2 are initialized to the RX/TX
activity encoding. The blink rate of the LEDs can be set by programming the BLINKRATE bit field
of the Ethernet PHY LED Control - MR24 (EPHYLEDCR) register, address 0x018
20.4.2.5 PHY Address
The integrated PHY's address is 0x00. To access the integrated PHY registers through the internal
MAC's MDIO interface, the PLA bit field of the Ethernet MAC MII Address (EMACMIIADDR) register
must be 0x00 and the MII field should be programmed to the desired address value.
20.4.2.6 Serial Management Interface
The Ethernet MAC module has the capability of programming the integrated PHY registers and
extended registers through an internal Serial Management Interface (SMI). The SMI is compatible
with IEEE802.3-2002 clause 22.
The SMI includes an MDC management clock input and management MDIO data pin to the Ethernet
PHY. The internal MDC clock is sourced by the system clock and then divided down to the required
2.5 MHz maximum clock frequency by setting the CR bit in the Ethernet MAC MII Address
(EMACMIIADDR) register. The MDC is not expected to be continuous, and can be turned off by
the external management entity when the bus is idle. The MDIO is sourced by the integrated MAC
and by the PHY. The data on the MDIO pin is latched on the rising edge of the MDC clock. The
PHY's physical address is 0x00.
20.4.2.7 Extended Address Space Access
The PHY SMI function supports read/write accesses to the extended register set using Ethernet
PHY Register Control - MR13 (EPHYREGCTL) register and the Ethernet PHY Address or Data
- MR14 (EPHYADDAR) registers. Accessing the standard register set, MDIO registers 0 to 31, can
be performed using the normal direct MDIO access or the indirect method, except for the
EPHYREGCTL (0x00D) and the EPHYADDAR (0x00E) which can be accessed only using the
normal MDIO transaction. The SMI function ignores indirect accesses to these registers.
The EPHYREGCTL register is the MDIO Manageable MMD access control. In general, register
EPHYREGCTL[4:0] is the device address DEVAD that directs any accesses of EPHYADDAR register
to the appropriate MMD. Specifically, the PHY uses the vendor specific DEVAD[4:0] = 0xF for
accesses. All accesses through registers EPHYREGCTL and EPHYADDAR registers should use
this DEVAD. Transactions with other DEVAD are ignored. The EPHYREGCTL[15:14] register holds
the access function:
■ EPHYREGCTL[15:14] = 0x0: A write to EPHYADDAR modifies the extended register set address
register. This address register must be initialized in order to access any of the registers within
the extended register set.
■ EPHYREGCTL[15:14] = 0x1: A read/write to EPHYADDAR operates on the register within the
extended register set selected (pointed to) by the value in the address register. The address
register contents (pointer) remain unchanged.
■ EPHYREGCTL[15:14] = 0x2: A read/write to EPHYADDAR operates on the register within the
extended register set selected (pointed to) by the value in the address register. After that access
is complete, for both reads and writes, the value in the address register is incremented.
■ EPHYREGCTL[15:14] = 0x3: A read/write to EPHYADDAR operates on the register within the
extended register set selected (pointed to) by the value in the address register. After that access
is complete, for write accesses only, the value in the address register is incremented. For read
accesses, the value of the address register remains unchanged.
June 18, 20141460
Texas Instruments-Production Data
Ethernet Controller
To Next Page
Loading...
Need help?
General
