The following sections describe how to perform operations on the extended register set using the
EPHYREGCTL and EPHYADDAR registers.
Write to PHY Registers
The following describes the steps to write to a PHY register.
1. Check the MIIB bit in the EMACMIIADDR register to identify if the MII interface is busy. When
the MIIB bit is 0, the MII interface is available to write to the PHY registers.
2. Write the data to be written to the PHY register in the EMACMIIDATA register.
3. Initiate write by programming the EMACMIIADDR register fields as follows:
■ PLA: Physical Layer Address of the PHY. The integrated PHY's address is 0x0.
■ MII: Address of the PHY register to be written.
■ CR: Clock Reference for the MDIO interface.
■ MIIW: Write Initiation. This bit is set to 1 to indicate that a write operation is to be executed.
■ MIIB: MII Busy. This bit is set to 1 to indicate that the MII is now busy with a write operation.
The EMAC clears this bit when the write has been transmitted.
Write to Extended PHY Registers
The following describes the steps to write to an extended PHY register.
1. Check the MIIB bit in the EMACMIIADDR register to identify if the MII interface is busy. When
the MIIB bit is 0, the MII interface is available to write to the PHY registers.
2. The EMACMIIDATA register should be written with the value to be passed into the
EPHYREGCTL register. The EPHYREGCTL register is used for extended PHY register accesses.
The DEVAD field of the EPHYREGCTL register identifies the device address, which is 0x1F, for
the integrated PHY. The FUNC field of the EPHYREGCTL register should be set to 0x0 to indicate
a write to an extended register address.
3. Initiate write by programming the EMACMIIADDR register fields as follows:
■ PLA: Physical Layer Address of the PHY. The integrated PHY's address is 0x0.
■ MII: Address of the PHY register to be written. In this case, it should be the address of the
EPHYREGCTL register, 0xD.
■ CR: Clock Reference for the MDIO interface.
■ MIIW: Write Initiation. This bit is set to 1 to indicate that a write operation is to be executed.
■ MIIB: MII Busy. This bit is set to 1 to indicate that the MII is now busy with a write operation.
The EMAC clears this bit when the write has been transmitted.
4. Check the MIIB bit in the EMACMIIADDR register to identify if the MII interface is busy. When
the MIIB bit is 0, the MII interface is available to write to the PHY registers.
1461June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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