DescriptionResetTypeNameBit/Field
Priority Ratio
These bits control the priority ratio in the weighted round-robin arbitration
between the RX DMA and TX DMA. These bits are valid only when the
DA bit in this register is clear. The priority ratio is RX:TX or TX:RX
depending on whether the TXPR bit in this register is clear or set.
DescriptionValue
The Priority Ratio is 1:1.0x0
The Priority Ratio is 2:1.0x1
The Priority Ratio is 3:1.0x2
The Priority Ratio is 4:1.0x3
0x0RWPR15:14
Programmable Burst Length
These bits indicate the maximum number of beats to be transferred in
one DMA transaction.
This is the maximum value that is used in a single block read or write.
The DMA always attempts to burst as specified in PBL each time it starts
a burst transfer on the bus. PBL can be programmed with permissible
values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined
behavior. When USP is set high, this PBL value is applicable only for TX
DMA transactions.
If the number of beats to be transferred is more than 32, then perform
the following steps:
1. Set the 8xPBL mode.
2. Set the PBL value.
For example, if the maximum number of beats to be transferred is 64,
then first set 8xPBL to 1 and then set PBL to 0x8.
0x1RWPBL13:8
Alternate Descriptor Size
DescriptionValue
Descriptor size reverts back to four words0
Alternate descriptors, each eight words in length, are used.1
0x0RWATDS7
Descriptor Skip Length
This bit specifies the number of words to skip between two unchained
descriptors.
The address skipping starts from the end of current descriptor to the
start of next descriptor. When the DSL value is equal to zero, then the
descriptor table is taken as contiguous by the DMA in Ring mode.
0x0RWDSL6:2
1555June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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