DescriptionResetTypeNameBit/Field
DMA Arbitration Scheme
This bit specifies the arbitration scheme between the transmit and receive
paths of the DMA channel.
DescriptionValue
Weighted round-robin with RX:TX or TX:RX.
The priority between the paths is according to the priority
specified in the PR bit field and priority weights specified in the
TXPR bit.
0
Fixed priority.
The transmit path has priority over receive path when the TXPR
bit is set. Otherwise, receive path has priority over the transmit
path.
1
0x0RWDA1
DMA Software Reset
The software reset function is driven by this bit.
The reset operation is completed only when all resets in all active clock
domains are deasserted. It is essential that all the PHY input clocks are
present for the software reset completion. The time of the software reset
operation depends on the frequency of the slowest active clock.
DescriptionValue
Reset is completed. A value of 0 should be read before
reprogramming any MAC registers after a reset
0
MAC DMA Controller resets the logic and all internal registers
of the MAC. It is cleared automatically after the reset operation
has completed in all of the MAC clock domains.
1
0x1RWSWR0
June 18, 20141556
Texas Instruments-Production Data
Ethernet Controller
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