DescriptionResetTypeNameBit/Field
Received Process State
This field indicates the Receive DMA state. This field does not generate
an interrupt.
DescriptionValue
Stopped: Reset or stop receive command issued0x0
Running: Fetching receive transfer descriptor0x1
reserved0x2
Running: Waiting for receive packet0x3
Suspended: Receive descriptor unavailable0x4
Running: Closing receive descriptor0x5
Writing Timestamp0x6
Running: Transferring the receive packet data from receive
buffer to host memory
0x7
0x0RORS19:17
Normal Interrupt Summary
Normal Interrupt Summary bit value is the logical OR of the following
when the corresponding interrupt bits are enabled in EMACDMAIM
register:
■ EMACDMARIS register, bit [0]: Transmit Interrupt
■ EMACDMARIS register, bit[2]: Transmit Buffer Unavailable
■ EMACDMARIS register, bit[6]: Receive Interrupt
■ EMACDMARIS register, bit[14]: Early Receive Interrupt
Only unmasked bits (interrupts for which interrupt enable is set in the
EMACDMAIM register) affect the Normal Interrupt Summary bit.
This is a sticky bit and must be cleared (by writing 1 to this bit) each
time a corresponding bit, which causes NIS to be set, is cleared.
0x0RW1CNIS16
1563June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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