DescriptionResetTypeNameBit/Field
Receive Watchdog Timeout
DescriptionValue
No watchdog timeout event has occurred.0
Indicates a frame with length greater than 2,048 bytes is
received (10, 240 when Jumbo Frame mode is enabled).
This bit is cleared by writing a 1 to it.
1
0x0RW1CRWT9
Receive Process Stopped
DescriptionValue
No receive process stopped event has occurred.0
Indicates the receive process has entered the stopped state.
This bit is cleared by writing a 1 to it.
1
0x0RW1CRPS8
Receive Buffer Unavailable
DescriptionValue
No receive buffer unavailable event has occurred.0
Indicates the host owns the next descriptor in the receive list
and the DMA cannot acquire it. The receive process is
suspended.
This bit is cleared by writing a 1 to it.
1
To resume processing receive descriptors, the host should change the
ownership of the descriptor and issue a Receive Poll Demand command.
If no Receive Poll Demand is issued, the receive process resumes when
the next recognized incoming frame is received. This bit is set only when
the previous receive descriptor is owned by the DMA.
0x0RW1CRU7
Receive Interrupt
DescriptionValue
No frame reception complete event has occurred.0
A frame reception is complete. When reception is complete,
bit[31] of RDES1 (disable interrupt on completion) is reset in
the last descriptor, and the specific frame status information is
updated in the descriptor. The reception remains in the Running
state.
This bit is cleared by writing a 1 to it.
1
0x0RW1CRI6
Transmit Underflow
DescriptionValue
No transmit underflow event has occurred.0
Indicates the Transmit Buffer had an Underflow during frame
transmission. Transmission is suspended and an Underflow
Error TDES0[1] is set.
This bit is cleared by writing a 1 to it.
1
0x0RW1CUNF5
1565June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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