DescriptionResetTypeNameBit/Field
Receive Overflow
DescriptionValue
No receive overflow event has occurred.0
The receive buffer had an overflow during frame reception. If
the partial frame is transferred to the application, the overflow
status is set in RDES0[11].
This bit is cleared by writing a 1 to it.
1
0x0RW1COVF4
Transmit Jabber Timeout
DescriptionValue
No transmit jabber timeout event has occurred.0
The Transmit Jabber Timer expired, which happens when the
frame size exceeds 2,048 (10,240 bytes when Jumbo frame is
enabled).
When the Jabber Timeout occurs, the transmission process is
aborted and placed in the Stopped state. This causes the
Transmit Jabber Timeout TDES0[14] flag to assert.
This bit is cleared by writing a 1 to it.
1
0x0RW1CTJT3
Transmit Buffer Unavailable
DescriptionValue
No transmit buffer unavailable event has occurred.0
Indicates the host owns the next descriptor in the transmit list
and the DMA cannot acquire it. Transmission is suspended.
The transmit process state bits (TS[22:20]) explain the transmit
process state transitions.
This bit is cleared by writing a 1 to it.
1
To resume processing Transmit descriptors, the host should change
the ownership of the descriptor by setting TDES0[31] and then issue a
Transmit Poll Demand command.
0x0RW1CTU2
Transmit Process Stopped
DescriptionValue
Interrupt is inactive.0
Indicates transmission is stopped.1
0x0RW1CTPS1
Transmit Interrupt
This bit indicates that frame transmission is complete. When transmission
is complete, the Bit 31 (Interrupt on Completion) of TDES1 is reset in
the first descriptor, and the specific frame status information is updated
in the descriptor.
DescriptionValue
Frame transmission completion event has not occurred.0
Frame transmission is complete.
This bit is cleared by writing a 1 to it.
1
0x0RW1CTI0
June 18, 20141566
Texas Instruments-Production Data
Ethernet Controller
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