Texas Instruments TM4C1294NCPDT - Page 34

Register 15: EPI Non-Blocking Read Data 0 (EPIRPSTD0), offset 0x028 ............................................. 897
Register 16: EPI Non-Blocking Read Data 1 (EPIRPSTD1), offset 0x038 ............................................. 897
Register 17: EPI Status (EPISTAT), offset 0x060 ................................................................................ 899
Register 18: EPI Read FIFO Count (EPIRFIFOCNT), offset 0x06C ...................................................... 901
Register 19: EPI Read FIFO (EPIREADFIFO0), offset 0x070 ............................................................... 902
Register 20: EPI Read FIFO Alias 1 (EPIREADFIFO1), offset 0x074 .................................................... 902
Register 21: EPI Read FIFO Alias 2 (EPIREADFIFO2), offset 0x078 .................................................... 902
Register 22: EPI Read FIFO Alias 3 (EPIREADFIFO3), offset 0x07C ................................................... 902
Register 23: EPI Read FIFO Alias 4 (EPIREADFIFO4), offset 0x080 .................................................... 902
Register 24: EPI Read FIFO Alias 5 (EPIREADFIFO5), offset 0x084 .................................................... 902
Register 25: EPI Read FIFO Alias 6 (EPIREADFIFO6), offset 0x088 .................................................... 902
Register 26: EPI Read FIFO Alias 7 (EPIREADFIFO7), offset 0x08C ................................................... 902
Register 27: EPI FIFO Level Selects (EPIFIFOLVL), offset 0x200 ........................................................ 903
Register 28: EPI Write FIFO Count (EPIWFIFOCNT), offset 0x204 ...................................................... 905
Register 29: EPI DMA Transmit Count (EPIDMATXCNT), offset 0x208 ................................................. 906
Register 30: EPI Interrupt Mask (EPIIM), offset 0x210 ......................................................................... 907
Register 31: EPI Raw Interrupt Status (EPIRIS), offset 0x214 .............................................................. 909
Register 32: EPI Masked Interrupt Status (EPIMIS), offset 0x218 ........................................................ 911
Register 33: EPI Error and Interrupt Status and Clear (EPIEISC), offset 0x21C .................................... 913
Register 34: EPI Host-Bus 8 Configuration 3 (EPIHB8CFG3), offset 0x308 .......................................... 915
Register 35: EPI Host-Bus 16 Configuration 3 (EPIHB16CFG3), offset 0x308 ....................................... 918
Register 36: EPI Host-Bus 8 Configuration 4 (EPIHB8CFG4), offset 0x30C .......................................... 922
Register 37: EPI Host-Bus 16 Configuration 4 (EPIHB16CFG4), offset 0x30C ...................................... 925
Register 38: EPI Host-Bus 8 Timing Extension (EPIHB8TIME), offset 0x310 ......................................... 929
Register 39: EPI Host-Bus 16 Timing Extension (EPIHB16TIME), offset 0x310 ..................................... 931
Register 40: EPI Host-Bus 8 Timing Extension (EPIHB8TIME2), offset 0x314 ....................................... 933
Register 41: EPI Host-Bus 16 Timing Extension (EPIHB16TIME2), offset 0x314 ................................... 935
Register 42: EPI Host-Bus 8 Timing Extension (EPIHB8TIME3), offset 0x318 ....................................... 937
Register 43: EPI Host-Bus 16 Timing Extension (EPIHB16TIME3), offset 0x318 ................................... 939
Register 44: EPI Host-Bus 8 Timing Extension (EPIHB8TIME4), offset 0x31C ...................................... 941
Register 45: EPI Host-Bus 16 Timing Extension (EPIHB16TIME4), offset 0x31C .................................. 943
Register 46: EPI Host-Bus PSRAM (EPIHBPSRAM), offset 0x360 ....................................................... 945
Cyclical Redundancy Check (CRC) ............................................................................................ 946
Register 1: CRC Control (CRCCTRL), offset 0x400 ........................................................................... 950
Register 2: CRC SEED/Context (CRCSEED), offset 0x410 ................................................................ 952
Register 3: CRC Data Input (CRCDIN), offset 0x414 ......................................................................... 953
Register 4: CRC Post Processing Result (CRCRSLTPP), offset 0x418 ............................................... 954
General-Purpose Timers ............................................................................................................. 955
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 976
Register 2: GPTM Timer A Mode (GPTMTAMR), offset 0x004 ........................................................... 977
Register 3: GPTM Timer B Mode (GPTMTBMR), offset 0x008 ........................................................... 982
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 986
Register 5: GPTM Synchronize (GPTMSYNC), offset 0x010 .............................................................. 990
Register 6: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 993
Register 7: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 996
Register 8: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 999
Register 9: GPTM Interrupt Clear (GPTMICR), offset 0x024 ............................................................ 1002
Register 10: GPTM Timer A Interval Load (GPTMTAILR), offset 0x028 .............................................. 1004
June 18, 201434
Texas Instruments-Production Data
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