Register 11: GPTM Timer B Interval Load (GPTMTBILR), offset 0x02C .............................................. 1005
Register 12: GPTM Timer A Match (GPTMTAMATCHR), offset 0x030 ................................................ 1006
Register 13: GPTM Timer B Match (GPTMTBMATCHR), offset 0x034 ................................................ 1007
Register 14: GPTM Timer A Prescale (GPTMTAPR), offset 0x038 ..................................................... 1008
Register 15: GPTM Timer B Prescale (GPTMTBPR), offset 0x03C ..................................................... 1009
Register 16: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ......................................... 1010
Register 17: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ......................................... 1011
Register 18: GPTM Timer A (GPTMTAR), offset 0x048 ..................................................................... 1012
Register 19: GPTM Timer B (GPTMTBR), offset 0x04C ..................................................................... 1013
Register 20: GPTM Timer A Value (GPTMTAV), offset 0x050 ............................................................. 1014
Register 21: GPTM Timer B Value (GPTMTBV), offset 0x054 ............................................................ 1015
Register 22: GPTM RTC Predivide (GPTMRTCPD), offset 0x058 ...................................................... 1016
Register 23: GPTM Timer A Prescale Snapshot (GPTMTAPS), offset 0x05C ...................................... 1017
Register 24: GPTM Timer B Prescale Snapshot (GPTMTBPS), offset 0x060 ...................................... 1018
Register 25: GPTM DMA Event (GPTMDMAEV), offset 0x06C .......................................................... 1019
Register 26: GPTM ADC Event (GPTMADCEV), offset 0x070 ........................................................... 1022
Register 27: GPTM Peripheral Properties (GPTMPP), offset 0xFC0 ................................................... 1025
Register 28: GPTM Clock Configuration (GPTMCC), offset 0xFC8 ..................................................... 1027
Watchdog Timers ....................................................................................................................... 1028
Register 1: Watchdog Load (WDTLOAD), offset 0x000 .................................................................... 1032
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................. 1033
Register 3: Watchdog Control (WDTCTL), offset 0x008 ................................................................... 1034
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C ......................................................... 1036
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 ................................................ 1037
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ........................................... 1038
Register 7: Watchdog Test (WDTTEST), offset 0x418 ...................................................................... 1039
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 .................................................................... 1040
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ............................... 1041
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ............................... 1042
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ............................... 1043
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC .............................. 1044
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ............................... 1045
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ............................... 1046
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ............................... 1047
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ............................... 1048
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................. 1049
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................. 1050
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................. 1051
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC ................................ 1052
Analog-to-Digital Converter (ADC) ........................................................................................... 1053
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ........................................... 1077
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ......................................................... 1079
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 .................................................................... 1082
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C ................................................ 1085
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 .......................................................... 1089
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ............................................... 1091
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ......................................................... 1096
Register 8: ADC Trigger Source Select (ADCTSSEL), offset 0x01C ................................................. 1097
35June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller