is blocked, and the processor is prevented from loading the constant data and, therefore, inhibiting
correct execution. Therefore, using execute-only protection requires that literal data be handled
differently. There are three ways to address this:
1. Use a compiler that allows literal data to be collected into a separate section that is put into one
or more read-enabled flash blocks. Note that the LDR instruction may use a PC-relative address,
in which case the literal pool cannot be located outside the span of the offset, or the software
may reserve a register to point to the base address of the literal pool and the LDR offset is
relative to the beginning of the pool.
2. Use a compiler that generates literal data from arithmetic instruction immediate data and
subsequent computation.
3. Use method 1 or 2, but in assembly language, if the compiler does not support either method.
8.2.3.6 Read-Only Protection
Read-only protection prevents the contents of the flash block from being re-programmed, while still
allowing the content to be read by processor or the debug interface. Note that if a FMPREn bit is
cleared, all read accesses to the Flash memory block are disallowed, including any data accesses.
Care must be taken not to store required data in a Flash memory block that has the associated
FMPREn bit cleared.
The read-only mode does not prevent read access to the stored program, but it does provide
protection against accidental (or malicious) erasure or programming. Read-only is especially useful
for utilities like the boot loader when the debug interface is permanently disabled. In such
combinations, the boot loader, which provides access control to the Flash memory, is protected
from being erased or modified.
8.2.3.7 Permanently Disabling Debug
For extremely sensitive applications, the debug interface to the processor and peripherals can be
permanently disabled, blocking all accesses to the device through the JTAG or SWD interfaces.
With the debug interface disabled, it is still possible to perform standard IEEE instructions (such as
boundary scan operations), but access to the processor and peripherals is blocked.
The DBG0 and DBG1 bits of the Boot Configuration (BOOTCFG) register control whether the debug
interface is turned on or off.
The debug interface should not be permanently disabled without providing some mechanism, such
as the boot loader, to provide customer-installable updates or bug fixes. Disabling the debug interface
is permanent and cannot be reversed.
8.2.3.8 Interrupts
The Flash memory controller can generate interrupts when the following conditions are observed:
■ Programming Interrupt: Signals when a program or erase action is complete. (PRIS).
■ Access Interrupt: Signals when a program or erase action has been attempted on a 16-kB block
of memory that is protected by its corresponding FMPPEn bit. (ARIS).
■ EEPROM Interrupt
■ Pump Voltage Interrupt: Indicates if the regulated voltage of the pump went out of specification
during a Flash operation and the operation was terminated. (VOLTRIS).
611June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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